公开(公告)号：DE10053780A1

公开(公告)日：2002-05-16

申请号：DE10053780

申请日：2000-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  HAUSDOERFER BASTIAN ,  GRAHL ORTRUN

IPC: H01L21/311

Abstract: The invention relates to a method for structuring a silicon oxide layer. According to said method, a substrate comprising a silicon oxide layer with a mask is provided in a plasma reactor. The silicon oxide layer is exposed to a plasma which is produced from an etching gas containing at least one fluorocarbon compound that is selected from the group consisting of compounds of the empirical formula CxHyFz, wherein x = 1 to 5, y = 0 to 4 and z = 2 to 10. The process is optimised by direct switching between the etching and deposition modes, which is achieved by varying the potential difference between the substrate and the plasma.

公开(公告)号：DE10207131B4

公开(公告)日：2007-12-20

申请号：DE10207131

申请日：2002-02-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANGER DIRK ,  GOLDBACH MATTHIAS

IPC: G03F1/00 ,  G03C5/00 ,  H01L21/033 ,  H01L21/768

Abstract: A hard mask is produced from spacer structures. The spacer structures are formed from a conformal deposition on elevated structures produced lithographically in a projection process. The conformal deposition is etched back laterally on the elevated structures resulting in the spacer structures. The elevated structures between the spacer structures are subsequently etched away, so that the spacer structures remain in an isolated fashion as sublithographic structures of a hard mask with a doubled structure density compared with that originally produced in lithographic projection. In a regularly disposed two-dimensional array of structures in the hard mask for forming trenches-for instance for trench capacitors-the method achieves a doubling of the structure density in the array. A further iteration step is formed by forming further spacer structures on the first and second spacer structures, thereby achieving an even higher increase in structure density in the hard mask.

公开(公告)号：DE50210157D1

公开(公告)日：2007-06-28

申请号：DE50210157

申请日：2002-02-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS

IPC: H01L27/108 ,  H01L21/8242

Abstract: The invention relates to an electrode arrangement for charge storage with an external trench electrode (202; 406), embodied along the wall of a trench provided in a substrate (401) and electrically insulated on both sides in the trench by a first and a second dielectric (104; 405, 409); an internal trench electrode (201; 410), serving as counter-electrode to the external trench electrode (201; 406) and insulated by the second dielectric (104; 409) and a substrate electrode (201; 403), which is insulated by the first dielectric (104; 405) outside the trench, which serves as counter-electrode to the external trench electrode (202; 406) and is connected to the internal trench electrode (201; 410) in the upper trench region.

公开(公告)号：DE50209714D1

公开(公告)日：2007-04-26

申请号：DE50209714

申请日：2002-01-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS

IPC: H01L21/033 ,  H01L21/3065 ,  H01L21/302 ,  H01L21/308 ,  H01L21/311

Abstract: To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or into an etching gas. The additional substance is present in the mask layer or a concentration of the additional substance can be subsequently increased in the mask layer. During a subsequent etching process for patterning using the mask layer, the mask layer is removed at a reduced etching rate.

公开(公告)号：DE102005022084B3

公开(公告)日：2006-10-26

申请号：DE102005022084

申请日：2005-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS

IPC: H01L21/8242

Abstract: The method involves applying and structuring a covering layer (121) on two different areas (111, 112) of a semiconductor substrate (101) with a photolithographic mask, where a semiconductor component is arranged on the substrate. An ion implantation for doping of the two different areas results under two different implantation angles with respect to a surface (190) of the semiconductor substrate.

公开(公告)号：DE102005009019A1

公开(公告)日：2006-09-07

申请号：DE102005009019

申请日：2005-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  STOEMMER RALPH

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238

Abstract: Spacer structures of field effect transistor structures are enhanced at least in sections with immobile charge carriers. The charge accumulated in the spacer structures induces an enhancement zone of mobile charge carriers in the underlying semiconductor substrate. The enhancement zone reduces the resistance of a channel coupling between the respective source/drain region and a channel region of the respective field effect transistor structure, wherein the channel region being controlled by a potential of a gate electrode. Source/drain regions drawn back from the gate electrode of the field effect transistor structure reduce an overlap capacitance between the gate electrode and the respective source/drain regions. A method for fabricating transistor arrangements having n-FETs and p-FETs with enhanced spacer structures.

公开(公告)号：DE102005001291A1

公开(公告)日：2006-07-06

申请号：DE102005001291

申请日：2005-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  MIKOLAJICK THOMAS ,  GOLDBACH MATTHIAS ,  HECHT THOMAS

IPC: H01L27/115 ,  H01L21/8247

公开(公告)号：DE102005025951A1

公开(公告)日：2006-01-05

申请号：DE102005025951

申请日：2005-06-06

Applicant: INFINEON TECHNOLOGIES AG ,  NANYA TECHNOLOGY CORP KUEISHAN

Inventor： GOLDBACH MATTHIAS ,  JAKUBOWSKI FRANK ,  KOEPE RALF ,  LAY CHAO-WEN ,  SCHUPKE KRISTIN ,  SCHMIDT MICHAEL ,  HUANG CHENG CHIH

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78 ,  H01L31/062

Abstract: A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.

公开(公告)号：DE10333777A1

公开(公告)日：2005-03-03

申请号：DE10333777

申请日：2003-07-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS

IPC: H01L21/20 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8232 ,  H01L21/8242 ,  H01L27/108

Abstract: The present invention provides a method for fabricating a trench capacitor with an insulation collar ( 10; 10 a, 10 b) in a substrate ( 1 ), which is electrically connected to the substrate ( 1 ) on one side via a buried contact ( 15 a, 15 b; 70 ), having the steps of: providing a trench ( 5 ) in the substrate ( 1 ) using a hard mask ( 2, 3 ) with a corresponding mask opening; providing a capacitor dielectric ( 30 ) in the lower and central trench region, the insulation collar ( 10 ) in the central and upper trench region and an electrically conductive filling ( 20 ) in the lower and central trench region, the top side of the electrically conductive filling ( 20 ) being sunk in the upper trench region with respect to the top side of the substrate ( 1 ); providing a silicon nitride liner ( 40 ) above the hard mask ( 2, 3 ) and in the trench ( 5 ); providing a silicon liner ( 50 ) above the silicon nitride liner ( 40 ); carrying out an oblique implantation (I 1 ), as a result of which a shaded region ( 50 a) of the silicon liner ( 50 ) is made selectively removable with respect to the rest of the silicon liner ( 50 ) by means of an etching process; selectively removing the shaded region ( 50 a) of the silicon liner ( 50 ) by means of the etching process; oxidizing the rest of the silicon liner ( 50 ); carrying out a spacer etching at the oxidized rest of the silicon liner ( 50' ); and depositing and etching back a conductive filling ( 70 ) in order to form the buried contact.

公开(公告)号：DE10334841A1

公开(公告)日：2005-02-24

申请号：DE10334841

申请日：2003-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  KUDELKA STEPHAN

IPC: H01L21/311 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

Abstract: Production of a trench capacitor comprises providing a trench (5) in the substrate (1) using a hard mask (2, 3) with corresponding mask openings, providing a capacitor dielectric (30) in the trench and insulating collar (10) in the trench, providing an electrically conducting filler (20) in the trench to protrude over the upper side of the hard mask in the form of a plug, isotropically back-etching the part of the filler protruding over the upper side of the hard mask to a pre-determined thickness, forming a mask over the protruding part of the filler, removing the filler using the mask up to below the upper side of the insulating collar exposing the dielectric in a connecting region (KS), removing the exposed connecting region and the mask, and filling the trench with a further electrically conducting filler (20') to form a trenched contact.