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    TRENCH CAPACITOR AND CORRESPONDING METHOD OF PRODUCTION
    1.
    发明申请
    TRENCH CAPACITOR AND CORRESPONDING METHOD OF PRODUCTION 审中-公开
    抓斗电容器及相应方法

    公开(公告)号：WO03003462A3

    公开(公告)日：2003-03-20

    申请号：PCT/EP0206462

    申请日：2002-06-12

    Applicant: INFINEON TECHNOLOGIES AG ,  MANGER DIRK

    Inventor： MANGER DIRK

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/105 ,  H01L29/06

    CPC classification number: H01L27/10861 ,  H01L27/10829 ,  H01L27/10867 ,  H01L29/66181

    Abstract: The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electrode, a dielectric layer (10) on the trench wall as capacitor dielectric and a metallic filler material (30'') provided in the trench (2) as second electrode. Above the conducting metallic filling material (30'') a dielectric filling material (35) is provided in the trench (2) with a cavity (40) provided for mechanical tensions. The invention further relates to a corresponding method of production.

    Abstract translation: 本发明提供了一个严重的电容器，特别是用于在半导体存储单元的使用，具有沟槽（2），其在基底（1）形成的; 一个在所述基板（1）所规定的区域（1A）作为第一电容器电极; 在严重壁作为电容器电介质的介电层（10）; 和在沟槽（2）提供了一种用于金属填充材料（30“”）作为第二Kondensatorelektode; 其中，在所述导电性金属填充材料（30“”）上的槽（2）形成具有用于接收应力的空腔（40），一个dielektisches填充材料（35）。 此外，本发明提供了一种相应的制造方法。

    METHOD FOR PRODUCING A MEMORY CELL OF A MEMORY CELL FIELD IN A SEMICONDUCTOR MEMORY
    2.
    发明申请
    METHOD FOR PRODUCING A MEMORY CELL OF A MEMORY CELL FIELD IN A SEMICONDUCTOR MEMORY 审中-公开
    一种用于生产记忆电池技术领域的存储单元在半导体存储器

    公开(公告)号：WO03046920A3

    公开(公告)日：2003-08-14

    申请号：PCT/DE0204287

    申请日：2002-11-21

    Applicant: INFINEON TECHNOLOGIES AG ,  MANGER DIRK

    Inventor： MANGER DIRK

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/1087

    Abstract: According to the invention, a capacitor comprising an electrode (11) as a memory cell node and a second electrode (20) as a common counter-electrode of the memory cell field is formed in a semiconductor substrate and a field effect transistor (FET) is subsequently created above the capacitor. The aim of the invention is to create a memory cell comprising a capacitor with a vertical construction and a vertical FET situated above said capacitor that can be easily and more reliably produced in terms of the technology involved. To achieve this, two parallel first trenches (10) are etched to a first depth (13) in the semiconductor substrate, a web (11) that is connected by its narrow sides to the semiconductor substrate being formed between the two trenches. The web is severed at the lower end and is separated from the substrate. The suspended web (15) is then provided with a closed dielectric (19). After the trenches have been filled, the FET (23, 24, 25, 26) is applied and is connected to the web as a memory node.

    Abstract translation: 本发明，在将形成在半导体衬底中，具有电极（11）作为存储单元节点和第二电极（20）作为存储单元阵列的一个共同的反电极，然后将电容器上的电容器中，产生的场效应晶体管（FET），该对象是基于一个 以提供与电容器和顶部垂直FET，其与较少的努力的垂直结构的存储单元，并产生技术上可靠。 这是，在所述半导体基片实现的，两个平行的第一槽（10），具有第一深度（13）被蚀刻，其之间的腹板（11）形成，其在它的窄侧连接到半导体衬底和在其 底切断而从半导体基板分离。 自由悬挂的幅材（15）现在提供具有封闭电介质（19）。 FET的填充之后（23，24，25，26）施加并连接到网络作为存储节点。

    3.
    发明专利
    未知

    公开(公告)号：DE102006024735A1

    公开(公告)日：2007-10-18

    申请号：DE102006024735

    申请日：2006-05-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MANGER DIRK ,  BOUBEKEUR HOCINE ,  VERHOEVEN MARTIN ,  NAGEL NICOLAS ,  TATRY THOMAS ,  CASPARY DIRK ,  MARKERT MATTHIAS

    IPC: G03F7/11 ,  G03F7/09 ,  H01L21/033 ,  H01L21/768

    Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

    4.
    发明专利
    未知

    公开(公告)号：DE10321466B4

    公开(公告)日：2007-01-25

    申请号：DE10321466

    申请日：2003-05-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEIDL HARALD ,  MANGER DIRK ,  GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SLESAZECK STEFAN

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/94

    Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a "buried" collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

    9.
    发明专利
    未知

    公开(公告)号：DE10219398B4

    公开(公告)日：2007-06-06

    申请号：DE10219398

    申请日：2002-04-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MOLL HANS-PETER ,  MANGER DIRK ,  SCHLOESSER TILL

    IPC: H01L21/76 ,  H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8242

    Abstract: Production of a trench arrangement comprises forming trenches in a semiconductor substrate (1) by etching using a mask (15) having a first opening (28) and a second opening (29) corresponding to the depth of the trenches, and providing in the second opening above the substrate a region (5) made from a material having a reduced etching rate compared with the substrate.

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