公开(公告)号：GB2432244B

公开(公告)日：2008-10-08

申请号：GB0704416

申请日：2005-09-21

Applicant: INTEL CORP

Inventor： MADUKKARUMUKUMANA RAJESH ,  SCHOINAS IOANNIS T ,  KING KU-JEI ,  VEMBU BALAJI ,  NEIGER GILBERT ,  UHLIG RICHARD

IPC: G06F11/07 ,  G06F9/45

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

公开(公告)号：HK1098223A1

公开(公告)日：2007-07-13

申请号：HK07105612

申请日：2007-05-29

Applicant: INTEL CORP

Inventor： MADUKKARUMUKUMANA RAJESH ,  SCHOINAS IOANNIS T ,  KING KU-JEI ,  VEMBU BALAJI ,  NEIGER GILBERT ,  UHLIG RICHARD

IPC: G06F20090101

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.