公开(公告)号：JP2005346689A

公开(公告)日：2005-12-15

申请号：JP2004259781

申请日：2004-09-07

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WILSON JOHN H ,  SCHOINAS IOANNIS T ,  YOUSIF MAZIN S ,  RANKIN LINDA J ,  GRAWROCK DAVID W ,  GREINER ROBERT J ,  SUTTON JAMES A ,  VAID KUSHAGRA ,  WISEMAN WILLARD M

IPC: G06F21/24 ,  G06F1/00 ,  G06F9/445 ,  G06F9/46 ,  G06F12/14 ,  G06F15/163 ,  G06F15/177 ,  H04L9/00

CPC classification number: G06F21/575 ,  G06F21/44 ,  G06F21/445 ,  G06F21/50 ,  G06F21/606 ,  G06F21/64 ,  G06F21/71 ,  G06F2221/034

Abstract: PROBLEM TO BE SOLVED: To start a reliable environment in a system. SOLUTION: In one embodiment, this method include steps for: authenticating a start logic processor of the system; evaluating a reliable agent by the start logic processor when the start logic processor is authenticated; and starting the reliable agent by a plurality of processors of the system when the reliable agent is evaluated. In a prescribed embodiment, after the execution of the reliable agent, a secure kernel can be started. For example, the system can be a multiprocessor server system having partially or perfectly connected topology having arbitrary point-to-point interconnection. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：在系统中启动可靠的环境。 解决方案：在一个实施例中，该方法包括以下步骤：验证系统的起始逻辑处理器; 当开始逻辑处理器被认证时由起始逻辑处理器评估可靠代理; 以及当评估可靠代理时，由系统的多个处理器启动可靠代理。 在规定的实施例中，在执行可靠代理之后，可以启动安全内核。 例如，该系统可以是具有具有任意点对点互连的部分或完全连接的拓扑的多处理器服务器系统。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：BRPI1005092A2

公开(公告)日：2013-04-09

申请号：BRPI1005092

申请日：2010-12-16

Applicant: INTEL CORP

Inventor： CHERUKURI NAVEEN ,  BRZEZINSKI DENNIS W ,  SCHOINAS IOANNIS T ,  SHAYESTEH ANAHITA ,  KUMAR AKHILESH ,  AZIMI MANI

IPC: G06F12/08 ,  G06F12/12

公开(公告)号：GB2432244A

公开(公告)日：2007-05-16

申请号：GB0704416

申请日：2005-09-21

Applicant: INTEL CORP

Inventor： MADUKKARUMUKUMANA RAJESH ,  SCHOINAS IOANNIS T ,  KING KU-JEI ,  VEMBU BALAJI ,  NEIGER GILBERT ,  UHLIG RICHARD

IPC: G06F11/07 ,  G06F9/45

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

公开(公告)号：EP2786300A4

公开(公告)日：2015-08-05

申请号：EP11876509

申请日：2011-11-30

Applicant: INTEL CORP

Inventor： GROBMAN STEVEN L ,  SCHOINAS IOANNIS T

IPC: G06F21/83 ,  G06F21/00 ,  G06F21/60

CPC classification number: G06F21/602 ,  G06F21/83

Abstract: A series of touch panel key entries may be secured by shuffling touch entry coordinates. In one embodiment, the entries may be secured by applying a shuffling algorithm that replaces the true coordinates with other incorrect coordinates. Then the correct data may be reassembled in a secure environment.

公开(公告)号：DE102019128261A1

公开(公告)日：2020-06-18

申请号：DE102019128261

申请日：2019-10-21

Applicant: INTEL CORP

Inventor： HARRIMAN DAVID J ,  SCHOINAS IOANNIS T ,  SOOD KAPIL ,  MAKARAM RAGHUNANDAN ,  CHEN YU-YUAN

IPC: G06F13/38

Abstract: Es werden erste Daten gespeichert. Eine Anforderung für die ersten Daten wird von einer Kommunikationsvorrichtung über eine Verbindungsstrecke empfangen, die mit einer Kommunikationsvorrichtung aufgebaut ist. Eine Zugriffssteuermaschine mit einer Schaltungsanordnung soll den Zugriff auf die ersten Daten für die Kommunikationsvorrichtung auf der Basis eines Authentifizierungszustandes der Kommunikationsvorrichtung und eines Schutzzustandes der Verbindungsstrecke steuern.

公开(公告)号：GB2431757B

公开(公告)日：2008-09-10

申请号：GB0703503

申请日：2005-09-01

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS T ,  MADUKKARUMUKUMANA RAJESH ,  NEIGER GILBERT ,  UHLIG RICHARD ,  KING KU-JEI

IPC: G06F12/10 ,  G06F13/38 ,  G06F13/40

Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.

公开(公告)号：GB2414823A

公开(公告)日：2005-12-07

申请号：GB0421213

申请日：2004-09-23

Applicant: INTEL CORP

Inventor： WILSON JOHN H ,  SCHOINAS IOANNIS T ,  YOUSIF MAZIN S ,  RANKIN LINDA J ,  GRAWROCK DAVID W ,  GREINER ROBERT J ,  SUTTON JAMES A ,  VAID KUSHAGRA ,  WISEMAN WILLARD M

IPC: G06F21/24 ,  G06F1/00 ,  G06F9/445 ,  G06F9/46 ,  G06F12/14 ,  G06F15/163 ,  G06F15/177 ,  H04L9/00

Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.

公开(公告)号：DE112009000836T5

公开(公告)日：2011-04-28

申请号：DE112009000836

申请日：2009-03-31

Applicant: INTEL CORP

Inventor： CHERUKURI NAVEEN ,  SCHOINAS IOANNIS T ,  KUMAR AKHILESH ,  PARK SEUNGJOON ,  CHOU CHING-TSUN

IPC: G06F9/46 ,  G06F9/06 ,  G06F12/08 ,  H04L45/17

公开(公告)号：GB2432244B

公开(公告)日：2008-10-08

申请号：GB0704416

申请日：2005-09-21

Applicant: INTEL CORP

Inventor： MADUKKARUMUKUMANA RAJESH ,  SCHOINAS IOANNIS T ,  KING KU-JEI ,  VEMBU BALAJI ,  NEIGER GILBERT ,  UHLIG RICHARD

IPC: G06F11/07 ,  G06F9/45

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

公开(公告)号：GB2429555B

公开(公告)日：2008-08-27

申请号：GB0620519

申请日：2004-09-23

Applicant: INTEL CORP

Inventor： WILSON JOHN H ,  SCHOINAS IOANNIS T ,  YOUSIF MAZIN S ,  RANKIN LINDA J ,  GRAWROCK DAVID W ,  GREINER ROBERT J ,  SUTTON JAMES A ,  VAID KUSHAGRA ,  WISEMAN WILLARD M

IPC: G06F21/00 ,  G06F21/24 ,  G06F1/00 ,  G06F9/445 ,  G06F9/46 ,  G06F12/14 ,  G06F15/163 ,  G06F15/177 ,  G06F15/80 ,  H04L9/00