公开(公告)号：WO2006039057A3

公开(公告)日：2006-06-29

申请号：PCT/US2005031471

申请日：2005-09-01

Applicant: INTEL CORP ,  SCHOINAS IOANNIS ,  NEIGER GILBERT ,  MADUKKARUMUKUMANA RAJESH ,  KING KU-JEI ,  UHLIG RICHARD ,  ZAHIR ACHMED ,  YAMADA KOICHI

Inventor： SCHOINAS IOANNIS ,  NEIGER GILBERT ,  MADUKKARUMUKUMANA RAJESH ,  KING KU-JEI ,  UHLIG RICHARD ,  ZAHIR ACHMED ,  YAMADA KOICHI

IPC: G06F12/10

CPC classification number: G06F12/1081 ,  G06F12/1036 ,  G06F12/109

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract translation: 本发明的实施例是用于增强地址翻译性能的技术。 寄存器存储能力指示器以指示芯片组中的电路所支持的用于客户物理地址到主机物理地址的地址转换的能力。 多个多级页面表用于地址转换中的页面行进。 每个页表都有页面条目。 每个页表项至少具有与能力指示符所指示的能力相对应的条目说明符。

公开(公告)号：DE112005002405T5

公开(公告)日：2007-08-16

申请号：DE112005002405

申请日：2005-09-21

Applicant: INTEL CORP

Inventor： MADUKKARUMUKUMANA RAJESH ,  SCHOINAS IOANNIS ,  KING KU-JEI ,  VEMBU BALAJI ,  NEIGER GILBERT ,  UHLIG RICHARD

IPC: G06F11/07

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

公开(公告)号：GB2431757A

公开(公告)日：2007-05-02

申请号：GB0703503

申请日：2005-09-01

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS T ,  MADUKKARUMUKUMANA RAJESH ,  NEIGER GILBERT ,  UHLIG RICHARD ,  KING KU-JEI

IPC: G06F12/10 ,  G06F13/38 ,  G06F13/40

Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.

公开(公告)号：GB2432244B

公开(公告)日：2008-10-08

申请号：GB0704416

申请日：2005-09-21

Applicant: INTEL CORP

Inventor： MADUKKARUMUKUMANA RAJESH ,  SCHOINAS IOANNIS T ,  KING KU-JEI ,  VEMBU BALAJI ,  NEIGER GILBERT ,  UHLIG RICHARD

IPC: G06F11/07 ,  G06F9/45

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

公开(公告)号：HK1098223A1

公开(公告)日：2007-07-13

申请号：HK07105612

申请日：2007-05-29

Applicant: INTEL CORP

Inventor： MADUKKARUMUKUMANA RAJESH ,  SCHOINAS IOANNIS T ,  KING KU-JEI ,  VEMBU BALAJI ,  NEIGER GILBERT ,  UHLIG RICHARD

IPC: G06F20090101

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

公开(公告)号：DE112005002298B4

公开(公告)日：2018-09-06

申请号：DE112005002298

申请日：2005-09-01

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS ,  NEIGER GILBERT ,  MADUKKARUMUKUMANA RAJESH ,  KING KU-JEI ,  UHLIG RICHARD ,  ZAHIR ACHMED ,  YAMADA KOICHI

IPC: G06F12/10

Abstract: Vorrichtung, umfassend:ein Register (220), das einem Logikschaltkreis (224) ermöglicht, eine physische Gastadresse des Speicherdirektzugriffs (SDZ) in eine gegebene physische Hostadresse zu übersetzen; undeine Mehrebenen-Baumstruktur (222) von Seitentabellen (520, 530, 540),in der eine Vielzahl von Seitentabelleneinträgen (525, 535) in einer oder mehreren nicht zur niedrigsten Ebene gehörigen Seitentabellen (520, 530) gespeichert sind, wobei jeder Seitentabelleneintrag auf eine Seitentabelle auf einer niedrigeren Ebene in der Baumstruktur zeigt; undin der eine Vielzahl von physischen Hostadressen in einer oder mehreren Seitentabellen (540) auf der niedrigsten Ebene der Baumstruktur gespeichert sind, wobei zumindest ein erster Seitentabelleneintrag in der Vielzahl von Seitentabelleneinträgen (525, 535) auf eine erste virtuelle Maschinen-Domain zeigt, die eine erste Seitentabelle (540m) auf der niedrigsten Ebene aufweist, wobei zumindest ein zweiter Seitentabelleneintrag der Vielzahl von Seitentabelleneinträgen (525, 535) auf eine zweite virtuelle Maschinen-Domain zeigt, die eine zweite Seitentabelle (540o) auf der niedrigsten Ebene aufweist, wobei die erste und die zweite virtuelle Maschinen-Domain voneinander isoliert sind undwobei der Logikschaltkreis (224) eingerichtet ist, zu den Übersetzungszwecken die Baumstruktur (222) zu verwenden, um die physische Gastadresse des Speicherdirektzugriffs in die gegebene physische Hostadresse abzubilden.

公开(公告)号：GB2431757B

公开(公告)日：2008-09-10

申请号：GB0703503

申请日：2005-09-01

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS T ,  MADUKKARUMUKUMANA RAJESH ,  NEIGER GILBERT ,  UHLIG RICHARD ,  KING KU-JEI

IPC: G06F12/10 ,  G06F13/38 ,  G06F13/40

Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.

公开(公告)号：GB2432443B

公开(公告)日：2008-04-02

申请号：GB0704914

申请日：2005-09-01

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS T ,  NEIGER GILBERT ,  MADUKKARUMUKUMANA RAJESH ,  KING KU-JEI ,  UHLIG RICHARD ,  ZAHIR ACHMED R ,  YAMADA KOICHI

IPC: G06F12/10

公开(公告)号：DE112005002298T5

公开(公告)日：2007-09-27

申请号：DE112005002298

申请日：2005-09-01

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS ,  NEIGER GILBERT ,  MADUKKARUMUKUMANA RAJESH ,  KING KU-JEI ,  UHLIG RICHARD ,  ZAHIR ACHMED ,  YAMADA KOICHI

IPC: G06F12/10

公开(公告)号：GB2432443A

公开(公告)日：2007-05-23

申请号：GB0704914

申请日：2005-09-01

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS T ,  NEIGER GILBERT ,  MADUKKARUMUKUMANA RAJESH ,  KING KU-JEI ,  UHLIG RICHARD ,  ZAHIR ACHMED R ,  YAMADA KOICHI

IPC: G06F12/10

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.