-
公开(公告)号：US20160275920A1
公开(公告)日：2016-09-22
申请号：US14662603
申请日：2015-03-19
Applicant: Intel Corporation
Inventor： Michael Apodaca , Thomas A. Piazza , Bimal Poddar
CPC classification number: G09G5/39 , G06T1/60 , G06T15/005 , G06T15/40
Abstract: The introduction of an “out-of-memory” marker in the sorted tile geometry sequence for a tile may aid in handling out-of-memory frames. This marker allows hardware to continue rendering using the original data stream instead of the sorted data stream. This enables use of the original data stream allows the system to continue rendering without requiring any driver intervention. During the visibility generation/sorting phase, the number of memory pages required for storing the data for a rendering pass is continuously tracked. This tracking includes tracking the pages that are required even if the hardware had not run out-of-memory. This information can be monitored by a graphics driver and the driver can provide more memory pages for the system to work at full efficiency.
Abstract translation: 在瓦片的排序瓦片几何序列中引入“内存不足”标记可能有助于处理超出内存的帧。 该标记允许硬件使用原始数据流而不是排序的数据流继续渲染。 这使得能够使用原始数据流允许系统继续呈现而不需要任何驱动器干预。 在可见性生成/分类阶段期间，持续追踪存储渲染通过数据所需的存储器页数。 该跟踪包括跟踪所需的页面，即使硬件没有运行内存不足。 该信息可以由图形驱动程序监视，驱动程序可以为系统提供更多的内存页面，以便全面工作。
-
公开(公告)号：US12236519B2
公开(公告)日：2025-02-25
申请号：US18090810
申请日：2022-12-29
Applicant: INTEL CORPORATION
Inventor： Karthik Vaidyanathan , Michael Apodaca , Thomas Raoux , Carsten Benthin , Kai Xiao , Carson Brownlee , Joshua Barczak
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
-
公开(公告)号：US12229870B2
公开(公告)日：2025-02-18
申请号：US17982766
申请日：2022-11-08
Applicant: INTEL CORPORATION
Inventor： Michael Apodaca , Carsten Benthin , Kai Xiao , Carson Brownlee , Timothy Rowley , Joshua Barczak , Travis Schluessler
Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
-
公开(公告)号：US11948017B2
公开(公告)日：2024-04-02
申请号：US16896031
申请日：2020-06-08
Applicant: Intel Corporation
Inventor： Abhishek Venkatesh , Michael Apodaca , Stav Gurtovoy , John H. Feit , Mateusz Przybylski , David M. Cimini
Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device; and a central processing unit (CPU). In some examples, the CPU is configured to: execute a producer to issue graphics command application program interfaces (APIs); execute a driver to translate graphics command APIs into executable instructions; and based on an idle state of the producer, execute a command translation code segment of the producer to translate graphics command APIs into executable instructions. In some examples, the execution unit is coupled to the memory device, the execution unit to execute one or more of the executable instructions. In some examples, the producer includes multiple portions such as application code, graphics pipeline runtime code, and command translation code segment.
-
公开(公告)号：US20230094696A1
公开(公告)日：2023-03-30
申请号：US17484060
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Carlos Nava Rodriguez , Jonathan Hersh , Aditi Gautam , Yoav Harel , Benjamin Pletcher , Michael Apodaca
IPC: G06T15/00 , G06F12/0895 , G06T1/60
Abstract: Embodiments described herein are generally directed to a local cache structure within a shared function of a 3D pipeline that facilitates efficient caching of resource state. In an example, the cache structure is maintained within a sub-core of a GPU. The local cache structure includes (i) an SC having entries each containing a state of a binded resource, and (ii) a DSAT having entries each containing an index into the SC. The DSAT is tagged by SBTO values representing addresses of entries of a binding table. A request, including information indicative of an SBTO pointing to an entry within the binding table, is received for a state of a particular binded resource being accessed by a shared function of the 3D pipeline. Based on the SBTO and during a single access to the cache structure, a determination is made regarding whether the state of the particular binded resource is present.
-
Patent Agency Ranking
公开(公告)号：US11461959B2
公开(公告)日：2022-10-04
申请号：US16865587
申请日：2020-05-04
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Abhishek R. Appu , Jeffery S. Boles , Balaji Vembu , Michael Apodaca , Slawomir Grajewski , Gabor Liktor , David M. Cimini , Andrew T. Lauritzen , Travis T. Schluessler , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Kai Xiao , Ankur N. Shah , Altug Koker
Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.
-
公开(公告)号：US11461954B2
公开(公告)日：2022-10-04
申请号：US17223464
申请日：2021-04-06
Applicant: Intel Corporation
Inventor： Michael Apodaca , John Feit , David Cimini , Thomas Raoux , Konstantin Levit-Gurevich
IPC: G06T15/00
Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.
-
公开(公告)号：US11252370B2
公开(公告)日：2022-02-15
申请号：US16939742
申请日：2020-07-27
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Joydeep Ray , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Karthik Vaidyanathan , Prasoonkumar Surti , Michael Apodaca , Murali Ramadoss , Abhishek Venkatesh
IPC: H04N5/911
Abstract: Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.
-
公开(公告)号：US11132759B2
公开(公告)日：2021-09-28
申请号：US16237987
申请日：2019-01-02
Applicant: Intel Corporation
Inventor： Abhishek Venkatesh , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Prasoonkumar Surti
Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.
-
公开(公告)号：US20210263742A1
公开(公告)日：2021-08-26
申请号：US17195132
申请日：2021-03-08
Applicant: Intel Corporation
Inventor： Altug Koker , Michael Apodaca , Kai Xiao , Chandrasekaran Sakthivel , Jeffery S. Boles , Adam T. Lake , Abhishek R. Appu
Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.
-
-
-
-
-
-
-
-
-
Search Results
154
records
(took 0.035 seconds)
