公开(公告)号：JP2001210206A

公开(公告)日：2001-08-03

申请号：JP2000018089

申请日：2000-01-26

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OGIWARA ATSUSHI ,  OKA NAOMASA

IPC: B81B3/00 ,  H01H1/00 ,  H01H1/06 ,  H01H11/04 ,  H01H37/52

Abstract: PROBLEM TO BE SOLVED: To provide a thermo switch that can perform a normal switching operation even with an inclined movable contact, and method of manufacturing the same. SOLUTION: The thermo switch includes a movable piece 1 with a movable end, and a stationary piece 6 with separated stationary contacts 7a, 7b. The movable piece 1 has a flexible region 2, a thin film 5 of a different thermal expansion deposited on the flexible region 2, and a movable contact 4 formed on the movable end. The flexible region 2 is flexed by a temperature variation so as to move the movable contact 4 to switch the stationary contacts 7a, 7b. The stationary contacts 7a, 7b are respectively provided on X-shaped structures 6a, 6b.

公开(公告)号：JP2000309000A

公开(公告)日：2000-11-07

申请号：JP2000034077

申请日：2000-02-10

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： TOMONARI SHIGEAKI ,  KAWADA HIROSHI ,  YOSHIDA HITOSHI ,  OGIWARA ATSUSHI ,  NAGAO SHUICHI ,  KAMAKURA MASAARI ,  SAITO KIMIAKI ,  NOBUTOKI KAZUHIRO

IPC: B81B3/00 ,  B25J7/00 ,  B81C1/00 ,  F03G7/06 ,  F16K31/02 ,  F16K31/70 ,  H01H37/14 ,  H01H37/52

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that is low in electric power consumption and simple in manufacture, a semiconductor micro-actuator, semiconductor micro-valve and semiconductor micro-relay that use the above device, and a manufacturing method of semiconductor devices and a manufacturing method of semiconductor micro- actuators. SOLUTION: Flexible regions 2 are each connected at one end to a semiconductor board 3 as a frame via a heat insulating region 7, and at the other to a movable element 5. Each heat insulating region 7 consists of a heat insulating material of such a resin as a polyimide and a fluorine-contained resin. Each flexible region 2 is constituted of a thin portion 2S and a thin film 2M differing in the coefficient of thermal expansion. When a diffused resistor 6 formed on the obverse side of each thin portion 2S is heated up, the differential thermal expansion between the thin portion 2S and the thin film 2M displaces the flexible region 2 with the result that the movable element 5 is displaced relative to the semiconductor board 3.

公开(公告)号：JP2000228403A

公开(公告)日：2000-08-15

申请号：JP2849899

申请日：1999-02-05

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKUTO TAKASHI ,  OKA NAOMASA ,  OGIWARA ATSUSHI

IPC: H01L23/52 ,  H01L21/285 ,  H01L21/3205

Abstract: PROBLEM TO BE SOLVED: To reduce silicon nodules to be separated on the surface of an aluminum wiring. SOLUTION: This aluminum wiring forming method comprises a process in which an insulating layer 2 is formed on one primary surface of a semiconductor substrate 1, a process in which an aluminum wiring 3 containing silicon is formed on the insulating layer 2 by sputtering, and a process in which a passivation film 4 is formed on both the insulating layer 2 and the aluminum wiring 3. The thermal histories of processes carried out after sputtering for the formation of the aluminum wiring 3 are set within a temperature range of 380 to 400 deg.C.

公开(公告)号：JP2000174265A

公开(公告)日：2000-06-23

申请号：JP34247198

申请日：1998-12-02

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKUTO TAKASHI ,  OKA NAOMASA ,  OGIWARA ATSUSHI

IPC: H01L29/78 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To provide a vertical power MOSFET whose gate electrode has superior embeddability, and its manufacturing method. SOLUTION: A groove 10 is formed in such a manner that it penetrates the surface of an n+-type source area 4, the n+-type source area 4, a p-type well area 3 to the midway of an n-type silicon epitaxial layer 2. A gate electrode 6 is embedded in the groove 10 with a gate oxide film 5 formed on the inner circumferential surface of the groove 10 interposed. The groove 10 comprises a first groove 10a which is formed on the side of an n+-type silicon substrate 1 in the depthwise direction of the groove 10, and a second groove 10b which is formed in a manner to penetrate the surface of the n+-type source area 4 to the first groove 10a and of which opening area is larger than the first groove 10a. The first and second grooves 10a and 10b are of trench type.

公开(公告)号：JPH11340171A

公开(公告)日：1999-12-10

申请号：JP14139998

申请日：1998-05-22

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OGIWARA ATSUSHI ,  OKA NAOMASA ,  OKUTO TAKASHI

IPC: H01L21/304

Abstract: PROBLEM TO BE SOLVED: To maintain the smoothness of etching form with no decreased work speed when a semiconductor substrate is etched by sand blast, by, after the semiconductor substrate is etched with jetted, under high pressure, abrasive, jetting the abrasive under low pressure for etching. SOLUTION: A silicon substrate 1 of an opening part 22 of a resist 2 is etched by sand blast to a depth L1 (about 90% of desired depth L2). Here, an abrasive is jetted under high pressure (first process). Then, the etching is continued by sand blast while the jetting pressure of abrasive is lower than the first process (second process). In the first process, working to the depth L1 is done in a short time since the jetting pressure of abrasive is high for faster etching speed. In the second process, with lower jetting pressure, a chipping 12 caused in the first process is eliminated for a smooth etching surface 14. Here, etching completes in a short time as it is about 10% of the desired depth L2.

公开(公告)号：JPH10335457A

公开(公告)日：1998-12-18

申请号：JP14171297

申请日：1997-05-30

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA ,  KAMAKURA MASATOMO ,  OGIWARA ATSUSHI ,  OKUTO TAKASHI

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can adjust its resistive value accurately, and a method for manufacturing the semiconductor device. SOLUTION: Formed on a single crystal silicon substrate 1 is a thick silicon oxide film 2, on which is formed a polysilicon layer 3a. The layer 3a has such an impurity distribution that a phosphorus (P) concentration is increased as a depth from the film 2 increases, and has a trapezoidal shape having a shorter lower bottom side. Formed on the layer 3a is a silicon oxide film 4 so as to have a minimum thickness at an upper bottom end of the layer 3a, on which is further formed a polysilicon layer 3b so that an amount of phosphorus (P) is increased as it goes from the film 4 on the layer 3a upto the surface of the film 2. And an interlayer insulating film 5 is formed on a side of the substrate 2 provided with the layers 3a and 3b. The films 4 and 5 formed on the layers 3 and 3b are partially removed to be electrically connected to respective aluminum wiring electrodes 6a and 6b.

公开(公告)号：JPH10335446A

公开(公告)日：1998-12-18

申请号：JP14171697

申请日：1997-05-30

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OGIWARA ATSUSHI ,  OKA NAOMASA ,  OKUTO TAKASHI ,  KAMAKURA MASATOMO

IPC: H01L21/762 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a dielectric isolation substrate which can prevent generation of a void at a tip end of a V-shaped groove. SOLUTION: A polysilicon layer 5a is formed as deposited on a side of a single crystal silicon substrate 1 having a groove 1a made therein by a CD process using trichlorosilane and hydrogen gases as source gases. At this time, flow rates of the source gases, especially the flow rate of the trichlorosilane gas is adjusted so that a deposition rate of the polysilicon layer 5a is 2 μm/min. or less. Next, the flow rates of the source gases, especially, the flow rate of the trichlorosilane gas is increased to set the deposition rate at 2 μm/min. or more, under the condition of which an upper polysilicon layer 5b is deposited.

公开(公告)号：JPH0993105A

公开(公告)日：1997-04-04

申请号：JP24501095

申请日：1995-09-25

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： MIYAJIMA HISAKAZU ,  YAMAGUCHI SHUICHIRO ,  OGIWARA ATSUSHI ,  SUGIURA YOSHIYUKI

IPC: H03K17/78

Abstract: PROBLEM TO BE SOLVED: To prevent a steep on-state transition caused by an excessive optical current. SOLUTION: This relay is provided with a light emitting diode 1, a photo diode array 2, an output MOSFET 3, a 1st MOSFET 4 of normally-on type, a 1st high resistive element 5, and a 2nd high resistive element 6. Then a 2nd MOSFET 10 of a normally-off type relay is connected between an anode and a cathode of the photo diode array 2 and a resistive element 9 controlling the 2nd MOSFET 10 is connected between a cathode of the photo diode array 2 and a source of the output MOSFET 3.

公开(公告)号：JPH07122610A

公开(公告)日：1995-05-12

申请号：JP26684893

申请日：1993-10-26

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OGIWARA ATSUSHI

IPC: G01R31/28 ,  H01L21/331 ,  H01L21/66 ,  H01L21/761 ,  H01L29/73 ,  H01L29/732

Abstract: PURPOSE:To facilitate the determination of contact between an isolation layer and a substrate and the positional shift of a buried layer by forming a P-type diffusion test layer in parallel with an N-type buried layer and an N-type diffusion test layer formed sequentially on a P-type substrate. CONSTITUTION:An N -type epitaxial layer 9 and an N-type buried test layer 10 are formed on a P-type substrate 8 and an N -type diffusion test layer 13 is formed on the surface of the N -type epitaxial layer 9. At least one P-type diffusion test layer 11 is then formed using a surface position of the N -type epitaxial layer 9 spaced apart horizontally, by a predetermined distance, from the design position of the N-type buried test layer 10 as a design position. Thereafter, a semiconductor test pattern comprising an electrode 14 connected with the N -type test layer 13 and an electrode 12 connected with the P-type diffusion test layer 11 is formed in the wafer simultaneously with the main pattern of a PN junction isolation bipolar transistor. A decision can be made easily whether the P-type isolation layer of main pattern reached the P-type substrate 1 by checking conduction between the electrode 12 and the rear electrode 16.

公开(公告)号：JP2006156850A

公开(公告)日：2006-06-15

申请号：JP2004347794

申请日：2004-11-30

Applicant: Matsushita Electric Works Ltd ,  松下電工株式会社

Inventor： USHIYAMA NAOKI ,  OGIWARA ATSUSHI ,  HARADA HIROSHI ,  OKA NAOMASA ,  YOSHIHARA TAKAAKI ,  KONO KIYOHIKO

IPC: H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To provide an etching method which facilitates confirmation of end of etching without making a preliminary test, and suppresses or prevents the microloading effect and deformation caused by side etching.
SOLUTION: In the etching method for etching a semiconductor substrate 1 to form a pattern, a pseudo pattern 3 is provided on the region of the semiconductor substrate 1 other than a region on which a desired pattern is formed, the end point of etching of the pseudo pattern 3 is monitored simultaneously with the etching, and the etching is terminated when the end point reaches a predetermined depth D.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在不进行初步试验的情况下便于确认蚀刻结束的蚀刻方法，并且抑制或防止由侧面蚀刻引起的微加载效应和变形。 解决方案：在用于蚀刻半导体衬底1以形成图案的蚀刻方法中，在除了形成期望图案的区域之外的半导体衬底1的区域上设置伪图案3， 蚀刻同时监视伪图案3的蚀刻，并且当端点达到预定深度D时，蚀刻终止。（C）2006，JPO和NCIPI