公开(公告)号：FR2840445A1

公开(公告)日：2003-12-05

申请号：FR0206794

申请日：2002-06-03

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  SCHOELLKOPF JEAN PIERRE

IPC: G06F11/10 ,  G11C29/00 ,  H04L1/22

Abstract: The memory circuit equipped with a system for error correction comprises an address (ADD) bus (102), an input data (DIN) bus (108), an output data (Dout) bus (115), a memory store (100) with an address bus (113), an input data (DinSP) bus (114), and an output data (DoutSP) bus (110), and a circuit for error correction comprising an encoder (107). The memory circuit also comprises an address register (104) connected to the address bus (102) and storing the addresses corresponding only to the write operations in the memory, a data register (105) connected to the input data bus (108) for storing the data transmitted to the encoder (107), and a multiplexer (103) allowing to introduce a shift of a cycle in the write operation without modifying the read operation, in a manner to permit a longer computing time for the encoder. The memory store (100) is RAM with single port (SP) and comprises an internal address register (101) and an internal data register (106). The multiplexer (103) comprises two inputs, one connected to the address bus (102) and the other to the output of the address register (104), a single output connected to the address bus (102) and the other to the output of the address register (104), a single output connected to the address bus (113) of the memory store (100), and a control input for a Write Enable Negative (WEN) signal, that is for authorizing the write operation. The memory circuit also comprises a comparator (109) with two inputs, one connected to the address bus (102) and the other to the output of the address register (104), and a single output (112) connected to the control input of the second multiplexer (111) with two inputs, one connected to the output of the data register (105) and the other to the output data bus (110) of the memory store (100), and a single output connected to the output data bus (115). The memory circuit (claimed) is in three embodiments. In the second embodiment, the memory circuit comprises an additional memory store which is double-port, and an ECC decoder. In the third embodiment, the memory circuit comprises a synchronous static memory store which is single-port, and an ECC decoder. The memory circuit comprises a synchronous static memory. The memory circuit comprises a system for error correction of type Single Error Correction Double Error Detection (SEC-DED) or Double Error Correction, Triple Error Detection (DEC-TED).

公开(公告)号：FR2817982B1

公开(公告)日：2003-10-24

申请号：FR0016035

申请日：2000-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS ,  MURILLO LAURENT

IPC: G06F11/20 ,  G11C7/00 ,  G11C29/00

Abstract: An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

公开(公告)号：FR2817982A1

公开(公告)日：2002-06-14

申请号：FR0016035

申请日：2000-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS ,  MURILLO LAURENT

IPC: G06F11/20 ,  G11C7/00 ,  G11C29/00

Abstract: Each allocation circuit (20) associated with memory bank (B) has means to switch the input/output lines (IOLi) as well as conductors (CTRL) for individual activation of read amplifiers (SA) of concerned memory bank. The allocation circuits comprise input/output line switches (IOLi) formed in same metallic level. The input/output lines and activation conductors (CTRL) are also formed in same metallic level. The lines and conductors are interrupted to right of each allocation circuit. Integrated memory circuit having at least two banks (B) each having a matrix of memory elements having at least a redundancy column and each associated with its own read amplifiers (SA); a row of input/output buffer circuits common to the memory banks; each memory bank has an allocation circuit (20), for the redundancy column, top an input/output line (IOLi) connected to one of the buffers. Allocation can be effected, for a line of a current row, towards the preceding row of columns and towards the following row of columns.