公开(公告)号：FR2814612B1

公开(公告)日：2003-02-07

申请号：FR0012225

申请日：2000-09-26

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT

IPC: H03M13/13 ,  H03M13/15 ,  H03M13/19 ,  H03M13/29 ,  G06F11/10 ,  H04L1/00

公开(公告)号：FR2899716A1

公开(公告)日：2007-10-12

申请号：FR0603074

申请日：2006-04-07

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT ,  GANIVET PHILIPPE

IPC: G11C16/22

Abstract: L'invention concerne un procédé de sécurisation d'une zone mémoire (MZ) comprenant des blocs de données (Wk), dans lequel on associe au moins deux bits témoins (CB0, CB1) à chaque bloc de données. Le procédé comprend une étape de lecture des bits témoins (CB0, CB1) associés à un bloc de données actuel (Wk) destiné à être remplacé par le nouveau bloc de données, avant l'écriture d'un nouveau bloc de données (Wk') dans la zone mémoire. Une action de sécurisation de la zone mémoire est engagée si les deux bits témoins (CB0, CB1) ont la même valeur. A chaque écriture d'un nouveau bloc de données (Wk') dans la zone mémoire, des bits témoins (CB0', CB1') ayant des valeurs inverses l'une de l'autre sont écrits dans la zone mémoire. Application notamment à la sécurisation d'un compteur binaire.

公开(公告)号：FR2830636A1

公开(公告)日：2003-04-11

申请号：FR0112862

申请日：2001-10-05

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT

IPC: H03M13/11 ,  H03M13/19 ,  G06F11/08

Abstract: The procedure for determining error detection bits includes forming the product of a vector with m components representative of the word of m bits to encode, and a parity control matrix (M). The parity control matrix comprises at least two consecutive columns which are complementary. The procedure for determining r error detection bits of a word of m bits to encode comprises a stage consisting of forming the product of a vector with m components representative of the word of m bits to encode, and a parity control matrix (M). The parity control matrix comprises at least two consecutive columns which are complementary. The binary representation of r-2 first bits of each column indicates the order of the column, with the exception of the of the first column, of order 0. The number, m, may be even, in which case the parity control matrix is such that the first half of the front-back line, corresponding to m/2 first columns, comprises a 0 at each end and 1s everywhere else. The second half of the front-back line, corresponding to m/2 columns, comprises a 1 at each end and 0s everywhere else. The last line is complementary to the front-back line.

公开(公告)号：DE602007012006D1

公开(公告)日：2011-03-03

申请号：DE602007012006

申请日：2007-03-15

Applicant: ST MICROELECTRONICS SA

Inventor： GANIVET PHILIPPE ,  MURILLO LAURENT

IPC: G11C7/20

公开(公告)号：FR2903205A1

公开(公告)日：2008-01-04

申请号：FR0605814

申请日：2006-06-28

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT ,  TAILLIET FRANCOIS

IPC: G06F1/14 ,  H03K19/003 ,  H03K19/177

Abstract: L'invention concerne un procédé de protection d'une machine d'état (FSM) ayant un fonctionnement modélisé par un ensemble d'états reliés entre eux par des transitions, la machine d'état évaluant à chaque transition durant une phase d'évaluation des signaux de sortie (PO, SO) en fonction de signaux d'entrée (PI, SI) comprenant des signaux (PI) évalués lors d'une transition précédente, le procédé comprenant des étapes de détermination d'une durée minimale de chaque phase d'évaluation en fonction d'une durée minimale nécessaire à l'évaluation des signaux de sortie (PO, SO) en fonction des signaux d'entrée (PI, SI ) , et d'ajustement de la durée de chaque phase d'évaluation.

公开(公告)号：FR2823035B1

公开(公告)日：2003-07-11

申请号：FR0104508

申请日：2001-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT ,  RICODEAU FRANCOIS

IPC: H03M13/19 ,  H03M13/00 ,  G06F11/10

Abstract: A method for determining r error detection bits that can be associated with a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix of dimension rxm. The parity control matrix is such that each column of matrix includes an odd number of " 1 s" greater than or equal to three. The present invention also relates to a method for determining a syndrome.

公开(公告)号：FR2830637A1

公开(公告)日：2003-04-11

申请号：FR0112863

申请日：2001-10-05

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT

IPC: H03M13/19 ,  G06F11/08

Abstract: The procedure for determining error detection bits uses a parity control matrix. This comprises at least two consecutive columns which are complementary. Furthermore, the matrix may be such that all the columns of the matrix are complementary with the exception of the just the first two columns. The procedure for determining r error detection bits of a word of m bits to encode comprises a stage consisting of forming the product of a vector with m components representative of the word of m bits to encode, and a parity control matrix (M). The parity control matrix comprises at least two consecutive columns which are complementary. The matrix may be such that all the columns of the matrix are complementary with the exception of the just the first two columns. In the event of m being even, with the exception of the first column of order 0 the binary representation of r-2 first elements of each column of even order (2i) corresponds to the order (i) of a pair (Ai) forming part of the column.

公开(公告)号：DE602007000870D1

公开(公告)日：2009-05-28

申请号：DE602007000870

申请日：2007-01-25

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLET FRANCOIS ,  MURILLO LAURENT

IPC: G01R31/3183

公开(公告)号：FR2899715A1

公开(公告)日：2007-10-12

申请号：FR0603076

申请日：2006-04-07

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT ,  GANIVET PHILIPPE

IPC: G11C16/20

Abstract: L'invention concerne un procédé d'initialisation d'un dispositif de contrôle (CTL) d'une mémoire (MEM), le dispositif de contrôle exécutant des commandes d'accès à la mémoire transmises à la mémoire par un signal de commande (DT) , le procédé comprenant des étapes de détection de la mise sous tension de la mémoire et d'initialisation au moins partielle du dispositif de contrôle à la suite de la mise sous tension de la mémoire. Selon l'invention, le procédé comprend des étapes de détection d'un événement particulier dans le signal de commande (DT), et d'initialisation au moins partielle du dispositif de contrôle (CTL) à la suite de la détection de l'événement particulier.

公开(公告)号：FR2823035A1

公开(公告)日：2002-10-04

申请号：FR0104508

申请日：2001-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT ,  RICODEAU FRANCOIS

IPC: H03M13/19 ,  H03M13/00 ,  G06F11/10

Abstract: The method for determining r error-detection bits which can be associated with a word of m bits for encoding, comprises a step of producing a vector of m components representative of the word of m bits and a parity-control matrix (M) of dimension rxm. The parity-control matrix (M) is such that each column of the matrix comprises an odd number of digit 1, where the number is greater than or equal to three. The last r-3 elements of each column of the matrix make part of a submatrix (Bi) of rank i, and the binary representation of the elements indicates the rank i of the sub-matrix. The sub-matrix (Bi) comprises sub-matrices of dimensions (r-3)x1 and sub-matrices of dimension (r-3)x3. The first three rows of the parity-control matrix comprise sub-matrices (Ai), which comprise sub-matrices of dimension 3x1 and sub-matrices of dimension 3x3; the former sub-matrices contain only digit 0 or digit 1, and the latter sub-matrices are either an identity matrix or its inverse. The sub-matrix (A0) is a sub-matrix of dimension 3x1 which contains only digit 1, and wherein other sub-matrices of dimension 3x1 contain only digit 0. The sub-matrix (Ai) of rank i has a number of columns equal to the number of columns of the sub-matrix (Bi) of the same rank. Two or more rows and/or columns of the parity-control matrix are permitted. The number r of error-detection bits is equal to n+2, where n is such that the number of bits of the word for encoding can be represented by n bits. The method for determining a syndrome representative of the errors eventually occurring in the course of processing is obtained at a step consisting of multiplying a particular matrix (M) of dimension rx(m+r) by a vector having m+r components representative of the rod of m+r bits, where the matrix comprises for m first columns a block of dimension rxm corresponding to the parity-control matrix utilized in coding, and for r last columns a block of dimension rxr in the form of a diagonal matrix, which contains digit 1 on the principal diagonal and digit 0 for other elements.