-
51.发明专利
公开(公告)号：FR2838861A1
公开(公告)日：2003-10-24
申请号：FR0205041
申请日：2002-04-23
Applicant: ST MICROELECTRONICS SA
Inventor： GANIVET FILIPE , GIOVINAZZI THIERRY , LA ROSA FRANCESCO
IPC: G11C16/30
Abstract: The memory store (MEM2) containing a memory array (MA) which comprises memory cells, also comprises a voltage supply managing circuit (PSMC) with a line (20) for distributing an internal supply voltage (Vps1) connected on one hand to a terminal (21) of an external voltage supply (Vcc) by the intermediary of a diode or a diode-simulation circuit (SDC), and on the other hand to a step-up voltage circuit (PMP3). The voltage supply managing circuit (PSMC) also comprises a regulator (REG3) for triggering the step-up voltage circuit (PMP3) when the internal supply voltage (Vps1) falls below a determined threshold (Vmin3), a slope generator (RAMPGEN) for progressively applying a higher voltage (Vpp), a gate generator (CGGEN) for generating the gate control voltage (Vcg), and a secondary voltage supply managing circuit (SPSMC) which comprises switches (SW1,SW2) in the form of MOS transistors, and inverters (11,12) connected to the gates of transistors. The internal supply voltage (Vps1) is maintained in the neighbourhood of the threshold (Vmin3) when the external supply voltage (Vcc) is too weak, at least during the reading of the memory cells when the diode-simulation circuit (SDC) remains blocked, that is in the off state. The threshold voltage (Vmin3) is greater or equal to the sum of the read voltage (Vread), or the drain polarization voltage (Vpol), and the threshold voltage (Vt) of MOS transistor. The step-up voltage circuit (PMP3) is for carrying the internal supply voltage (Vps1) to a higher voltage (Vpp) required for the erasing of the programming of memory cells. The step-up voltage circuit (PMP3) is of type charge pump. The memory store comprises a row decoder (RDEC) whose supply terminal (T1) is connected to the distribution line (20) of voltage (Vps1), and a column decoder (CDEC) whose supply terminal (T2) is connected to the secondary voltage (Vps2). The diode-simulation circuit (SDC) comprises a supply interrupter with a low voltage drop in the form of MOS transistor, and the means for controlling the interrupter with a low voltage drop in the form of MOS transistor, and the means for controlling the interrupter in the form of a differential circuit for comparing the external supply voltage and the internal supply voltage. A method (claimed) for managing the internal voltage supply is implemented by the device as claimed.
-
公开(公告)号：FR2809246B1
公开(公告)日：2003-08-15
申请号：FR0006262
申请日：2000-05-17
Applicant: ST MICROELECTRONICS SA
Inventor： LA ROSA FRANCESCO , TAILLIET FRANCOIS
-
Patent Agency Ranking
公开(公告)号：FR2832566A1
公开(公告)日：2003-05-23
申请号：FR0114969
申请日：2001-11-20
Applicant: ST MICROELECTRONICS SA
Inventor： LA ROSA FRANCESCO
Abstract: The present invention relates to a read amplifier (SA2) comprising a read stage (RDST), a reference stage (RFST) and a differential output stage comprising PMOS and NMOS type transistors. According to the present invention, the transistors of the differential stage (DIFST2) comprise only one PMOS transistor (TP3) and one NMOS transistor (TN3) in series, the PMOS transistor (TP3) having its gate linked to one node of the read stage (RDST), the NMOS transistor (TN3) having its gate linked to one node of the reference stage (RFST), the mid-point of the PMOS and NMOS transistors of the differential stage forming a data output node (DATAOUT) of the read amplifier. The read amplifier according to the present invention has the combined advantages of a short read time and a low electrical consumption. Application to EPROM, EEPROM and FLASH type non-volatile memories.
-
公开(公告)号：FR2825806A1
公开(公告)日：2002-12-13
申请号：FR0107482
申请日：2001-06-08
Applicant: ST MICROELECTRONICS SA
Inventor： LA ROSA FRANCESCO
IPC: G05F3/20 , G05F3/26 , G05F3/02 , H01L27/085 , H01L23/34
Abstract: The polarization circuit (20) integrated on a silicon wafer comprises the first branch (B1) with a p-MOS transistor (TP1) in series with an n-MOS transistor (TN1), the second branch (B2) with a p-MOS transistor (TP2) in series with an n-MOS transistor (TN2) and a resistance (R), and the third branch (B3) with a p-MOS transistor (TP3) in series with an n-MOS transistor (TN3). The two branches (B1,B2) are connected as a current-mirror circuit, and the gates of transistors (TN1,TN2) are connected to one another. The transistors (TP3,TN3) of the third branch are connected so to maintain the drain of the transistor (TP2) at a voltage substantially identical to the drain voltage of the transistor (TN1). The gate of the transistor (TP3) is connected to the drain of the transistor (TP2), and the gate of the transistor (TN3) is connected to the drain of the same transistor and to the gate of the transistor (TN1). The drain of the transistor (TP1) is connected to the gate of the same transistor. The resistance (R) is implemented by two resistors (R1,R2) connected in series or in parallel and having different temperature coefficients. The transistor (TN2) is implemented as a set of n-MOS transistors connected in parallel so to obtain an N-times higher value of the W/L ratio. The resistance (R) has a temperature coefficient selected so that the variation of the resistance with temperature ensures the temperature stability of the current (I2) through the second branch (B2). The resistors are implemented as doped regions of silicon: the first as n-type doped, and the second as n or p doped. The two resistances have the values R10 and R20 at ambient temperature which satisfy given relations expressing the resistances in terms of a resistance R0 and three temperature coefficients. The circuit delivers a reference voltage (Vref) on the gate of the transistor (TN1) as an output connected to the gate of an external transistor (TN0) connected in an external branch (Be). In the second embodiment, the circuit comprises an additional n-MOS transistor in each of the two branches (B1,B2) whose gates are connected together to the gate of the transistor (TN1).
-
公开(公告)号：FR2802734B1
公开(公告)日：2002-04-26
申请号：FR9915816
申请日：1999-12-15
Applicant: ST MICROELECTRONICS SA
Inventor： LA ROSA FRANCESCO
Abstract: The error correction procedure corrects an error in bit b2 in a sequence of bits b0 - b8. A parity bit (b8) is calculated from the other bits b1 - b7 at an instant where the erroneous bit (b2) was valid, and a second parity bit (b9) calculated from all the bits except the erroneous bit, to replace the erroneous bit.
-
公开(公告)号：FR2813462A1
公开(公告)日：2002-03-01
申请号：FR0010873
申请日：2000-08-23
Applicant: ST MICROELECTRONICS SA
Inventor： LA ROSA FRANCESCO
IPC: G11C7/22 , H03K19/003 , H03K17/14 , H03K5/14
Abstract: The integrated memory circuit comprises a memory array and a buffer circuit (20) for receiving an external clock signal (CLKEXT), the means for transferring the clock signal, and the means for transmitting the data read in the memory array in synchronism with the leading and/or trailing edges of the clock signal pulse. The buffer circuit (20) comprises the inverter gates (I1,I2) in series as in prior buffer circuits, and in addition a front-end detector (FED) delivering an inhibition signal (INHIB) of a determined duration when the clock signal (CLK) presents a leading and/or trailing edge, a transistor-interrupter (T1) for insulating the output from the input when the inhibition signal is delivered, and a memory circuit including an inverter gate (I3) and a transistor-interrupter (T2) for maintaining a logic value at the output which is present when the inhibition signal is delivered. The inhibition signal (INHIB) is applied to the gate of the transistor-interrupter (T1) by the intermediary of an inverter gate (I4), and the front-end detector (FED) receives the clock signal from the output by the intermediary of an AND gate (21), which receives on one input the clock signal and on the other input a validation signal (VALID). The front-end detector (FED) contains a delay line with three inverter gates in series connected to the inverted input of a NOR gate, which receives the clock signal at the direct input. The first and second transistors-interrupters (T1,T2) are controlled by mutually inverted signals so that when the first is nonconducting, the second is conducting, and vice versa. The inhibition signal is transmitted only in the periods of data transmission.
-
公开(公告)号：FR2802697A1
公开(公告)日：2001-06-22
申请号：FR9915819
申请日：1999-12-15
Applicant: ST MICROELECTRONICS SA
Inventor： LA ROSA FRANCESCO
Abstract: The method for reading a vit recorded in a memory cell (CELL) of ROM type, comprises a step of sensing a remanent electrical characteristic, that is drain current versus threshold voltage, (Vt, Id) of cell representative of the bit value, by attributing a first logic value (1) to the bit when the remanent characteristic of cell is greater than a first threshold given by a reference current (Iref (1)), a second logic value (0) when the remanent characteristic is less than a second threshold (Iref (0)), which is lower than the first theshold, and by considering the bit as erroneous (Sx = 1) when the remanent characteristic is between the first and the second thresholds. A predetermined logic value (0) is attributed to the bit when the remanent characteristic is between the thresholds, while considering the bit as erroneous. An erroneous bit (b2) is corrected by computing the good value of bit by means of other bits (b1, b3-b8) from the sequence of 8 bits read in memory, where the sequence comprises at least one error-correcting bit (b8) computed on the basis of other bits (b1-b7) at an instant when the erroneous bit is valid. The error correcting bit (b8) is a parity bit, and the erroneous bit (b2) is corrected by replacing the erroneous bit by a parity bit (b9), which is computed as a function of bits other than the erroneous bit. A logic value (0) is attributed to the erroneous bit without affecting the parity computation, and the parity bit (b9) is computed on the basis of all bits (b1-b8) from the sequence of 8 bits comprising the erroneous bit. The memory cell (CELL) comprises a floating-gate transistor (FGT), the bit is read by the application of a read voltage (Vread) to the gate of transistor, and by comparing the current (Id) through the transistor to two reference currents (Iref (0), Iref (1)); the bit is considered as erroneous when the current is between the two reference currents. Several bits (b1-b7) from the sequence of 8 bits stored in memory are read simultaneously for correcting a bit in the sequence. The first and second thresholds define a region containing the domain of blank cells or contained in it, so that the error state of a bit remains stable in time. The method for reading a binary word in a memory of ROM type comprising a set of memory cells, is characterized that at least a part of bits constituting the binary word is read according to the proposed method. A memory of ROM type comprising memory cells arranged in rows and columns, also comprises means (SA3) for reading the memory cells in the form of sense amplifier, and as correction circuit incorporating a parity computation circuit (PCC). The memory comprises floating-gate transistors and means (SA2) for comparing the current through a cell to two reference currents, which signals the error when the current is between the two reference currents.
-
-
-
-
-
-
Search Results
57
records
(took 0.025 seconds)
