公开(公告)号：EP1519489A1

公开(公告)日：2005-03-30

申请号：EP03021455.5

申请日：2003-09-23

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  De Sandre, Guido ,  Bez, Roberto

IPC: H03K19/177

CPC classification number: G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

Abstract: The present invention proposes a Field Programmable Gate Array (FPGA) device (100) comprising a plurality of configurable electrical connections (115 1 -115 2 ,115 1 -115 3 ), a plurality of controlled switches (205), each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit (125) including an arrangement of a plurality of control cells (200). Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element (210,215) adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element (P1;F1) coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

Abstract translation: 本发明提出了一种包括多个可配置电连接（1151-1152,1151-1153）的现场可编程门阵列（FPGA）装置，多个受控开关（205），每个控制开关适于启动/ 响应于开关控制信号激活至少一个相应的电连接，以及包括多个控制单元（200）的布置的控制单元（125）。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件（210,215），其适于以易失性方式存储对应于至少一个 控制开关，并且向控制开关提供与存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件（P1; F1），非易失性存储元件适于以非易失性方式存储控制逻辑值。

公开(公告)号：EP1439583A9

公开(公告)日：2005-03-16

申请号：EP03425016.7

申请日：2003-01-15

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Khouri, Osama, ,  Pollaccia, Giorgio ,  Pellizzer, Fabio

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A contact structure (98) for a PCM device is formed by an elongated formation (102) having a longitudinal extension parallel to the upper surface (92) of the body (91) and an end face (110) extending in a vertical plane. The end face (110) is in contact with a bottom portion of an active region (103) of chalcogenic material so that the dimensions of the contact area defined by the end face (110) are determined by the thickness (S) of the elongated formation and by the width (W) thereof.

公开(公告)号：EP1469532A1

公开(公告)日：2004-10-20

申请号：EP03425235.3

申请日：2003-04-16

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Pellizzer, Fabio

IPC: H01L45/00 ,  H01L27/24 ,  G11C11/34 ,  H01L27/10

CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/101 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

Abstract: A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element (22); forming a delimiting structure (48, 49, 55a) having an aperture (56) over the resistive element (22); forming a memory portion (38a) of a phase change material in the aperture, the resistive element (22) and the memory portion (38a) being in direct electrical contact and defining a contact area (58) of sublithographic extension. The step of forming a memory portion (38a) further includes filling the aperture (56) with the phase change material and removing from the delimiting structure (48, 49, 55a) an exceeding portion (38b) of the phase change material exceeding the aperture (56).

Abstract translation: 一种用于制造相变存储单元的方法，包括以下步骤：形成一电阻元件（22）; 上形成具有开口（56）在所述电阻元件（22）上的限制结构（48,49，55A）; 形成相变材料的孔中的存储器部分（38A），电阻元件（22）和存储部分（38A）直接电接触和限定亚光刻延伸的接触区域（58）。 形成存储器部分（38A）还包括填充与相变材料中的孔（56）和从所述限制结构（48,49，55A）上超过部分中的相变材料的（38B）超过孔径去除步骤 （56）。

公开(公告)号：EP1339111A9

公开(公告)日：2004-01-28

申请号：EP02425089.6

申请日：2002-02-20

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Pellizzer, Fabio

IPC: H01L45/00 ,  H01L27/24

CPC classification number: G11C11/5678 ,  G11C11/56 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y); and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) which is transverse to said first direction. The first and second thin portions (22, 38a) are in direct electrical contact and define a contact area (58) having sublithographic extent. The second thin portion (38a) is formed in a slit of sublithograhic dimensions. According to a first solution, oxide spacer portions (55a) are formed in a lithographic opening (51), delimited by a mold layer (49). According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

公开(公告)号：EP1339103A1

公开(公告)日：2003-08-27

申请号：EP02425088.8

申请日：2002-02-20

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Casagrande, Giulio ,  Bez, Roberto ,  Pellizzer, Fabio

IPC: H01L23/522 ,  H01L23/528 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: An electronic semiconductor device has a sublithographic contact area (45, 58) between a first conductive region (22) and a second conductive region (38). The first conductive region (22) is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area (45, 58). The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract translation: 一种电子半导体器件具有第一导电区（22）和一个第二导电区（38）之间的亚光刻的接触面积（45，58）。 第一导电区（22）是杯形，并具有垂直壁延伸，在俯视图中，沿着细长形状的封闭线。 一个第一导电区域的壁的形成第一薄壁部，并且具有在第一方向上的第一尺寸。 第二导电区域（38）具有在第二方向上的第二亚光刻尺寸（X）横向于第一尺寸的第二薄壁部（38A）。 所述第一和第二导电区域在其薄的部分直接电接触，并形成亚光刻接触区域（45，58）。 细长形状在第一方向上的矩形和椭圆形的细长之间选择。 因此，接触区域的尺寸，即使在掩模之间的小的未对准的存在保持大致恒定，限定导电区域。