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    Semiconductor Structure with Inhomogeneous Regions
    53.
    发明申请
    Semiconductor Structure with Inhomogeneous Regions 有权
    具有不均匀区域的半导体结构

    公开(公告)号：US20140239312A1

    公开(公告)日：2014-08-28

    申请号：US14189012

    申请日：2014-02-25

    Applicant: Sensor Electronic Technology, Inc.

    Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Alexander Lunev ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

    IPC: H01L33/32

    CPC classification number: H01L33/0025 ,  H01L33/0075 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01S5/0224

    Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher.

    Abstract translation: 提供包括多个不均匀区域的半导体层。 每个不均匀区域具有与形成半导体层的材料不同的一个或多个属性。 不均匀区域可以包括基于具有目标波长的辐射配置的一个或多个区域。 这些区域可以包括透明和/或反射区域。 不均匀区域还可以包括具有比基于辐射的区域的电导率更高的导电率的一个或多个区域，例如至少高10％。

    Epitaxy Technique for Reducing Threading Dislocations in Stressed Semiconductor Compounds
    54.
    发明申请
    Epitaxy Technique for Reducing Threading Dislocations in Stressed Semiconductor Compounds 审中-公开
    降低半导体化合物中螺旋位错的外延技术

    公开(公告)号：US20130193480A1

    公开(公告)日：2013-08-01

    申请号：US13756806

    申请日：2013-02-01

    Applicant: Sensor Electronic Technology, Inc.

    Inventor： Wenhong Sun ,  Rakesh Jain ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

    IPC: H01L21/02 ,  H01L29/06

    CPC classification number: H01L21/02587 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/0684 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/16

    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.

    Abstract translation: 提供了一种用于制造半导体结构的解决方案。 半导体结构包括使用一组外延生长周期在衬底上生长的多个半导体层。 在每个外延生长周期期间，生长具有拉伸应力或压缩应力之一的第一半导体层，然后直接在第一半导体层上生长具有另一个的拉伸应力或压缩应力的第二半导体层。 一组生长条件中的一个或多个层中的一个或两个的厚度和/或层之间的晶格失配可以被配置为在最小百分比的范围内产生压缩和/或剪切应力的目标水平 层之间的界面。

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