公开(公告)号：US11764120B2

公开(公告)日：2023-09-19

申请号：US17155094

申请日：2021-01-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Pei-Chi Chen ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/49827

Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.

公开(公告)号：US11665832B2

公开(公告)日：2023-05-30

申请号：US17234805

申请日：2021-04-20

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/20 ,  H05K3/36 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  H05K3/02

CPC classification number: H05K3/46 ,  H05K3/022 ,  H05K3/386 ,  H05K3/4038

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

公开(公告)号：US11476234B2

公开(公告)日：2022-10-18

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/00 ,  H01L33/52

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US20220256717A1

公开(公告)日：2022-08-11

申请号：US17234805

申请日：2021-04-20

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K3/46 ,  H05K3/02 ,  H05K3/40 ,  H05K3/38

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

公开(公告)号：US20220208631A1

公开(公告)日：2022-06-30

申请号：US17156626

申请日：2021-01-24

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.

公开(公告)号：US11127664B2

公开(公告)日：2021-09-21

申请号：US15391861

申请日：2016-12-28

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Kai-Ming Yang ,  Wang-Hsiang Tsai ,  Tzyy-Jang Tseng

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H05K3/46 ,  H01L23/14 ,  H01L23/15

Abstract: A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.

公开(公告)号：US20210282275A1

公开(公告)日：2021-09-09

申请号：US16847688

申请日：2020-04-14

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin

IPC: H05K3/46 ,  H05K3/22 ,  H05K1/02

Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.

公开(公告)号：US10897823B2

公开(公告)日：2021-01-19

申请号：US16361180

申请日：2019-03-21

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Chih-Lun Wang

IPC: H05K1/18 ,  H05K1/09 ,  H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46

Abstract: A circuit board including an interconnect substrate and a multilayer structure is provided. The interconnect substrate includes a core layer and a conductive structure disposed on the core layer. The multilayer structure is disposed on the conductive structure. The multilayer structure includes a plurality of dielectric layers and a plurality of circuit structures. The circuit structures are disposed in the dielectric layers. A topmost layer in the circuit structures is exposed to the dielectric layers to be in contact with the conductive structure. A pattern of the topmost layer in the circuit structures and a pattern of a top surface of the conductive structure are engaged with each other.

公开(公告)号：US10756050B2

公开(公告)日：2020-08-25

申请号：US16152424

申请日：2018-10-05

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen

IPC: H01L29/40 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package structure is also provided.