公开(公告)号：US11166387B2

公开(公告)日：2021-11-02

申请号：US16847688

申请日：2020-04-14

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K3/22

Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.

公开(公告)号：US20240248264A1

公开(公告)日：2024-07-25

申请号：US18623035

申请日：2024-04-01

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: G02B6/42 ,  G02B6/12 ,  H01L23/498 ,  H01L25/065

CPC classification number: G02B6/4206 ,  G02B6/12004 ,  G02B6/4293 ,  H01L23/49816 ,  H01L25/0652

Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

公开(公告)号：US11895780B2

公开(公告)日：2024-02-06

申请号：US17194323

申请日：2021-03-08

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Wang-Hsiang Tsai ,  Cheng-Ta Ko

IPC: H05K3/46 ,  H05K3/40 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18 ,  H05K1/14 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/36 ,  H01L23/00 ,  H01L21/683 ,  H05K1/02

CPC classification number: H05K3/4038 ,  H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/36 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K3/4644 ,  H05K3/4673 ,  H01L23/145 ,  H01L23/49816 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H05K1/0271 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

Abstract: A method of manufacturing package structures includes providing a carrier including a supporting layer, a metal layer, and a release layer between the supporting layer and the metal layer at first. Afterwards, a composite layer of a non-conductor inorganic material and an organic material is disposed on the metal layer. Then, a chip embedded substrate is bonded on the composite layer. Afterwards, an insulating protective layer having openings is formed on the circuit layer structure and exposes parts of the circuit layer structure in the openings. Afterwards, the supporting layer and the release layer are removed to form two package substrates. Then, each of the package substrates is cut.

公开(公告)号：US20210282275A1

公开(公告)日：2021-09-09

申请号：US16847688

申请日：2020-04-14

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin

IPC: H05K3/46 ,  H05K3/22 ,  H05K1/02

Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.

公开(公告)号：US20240251504A1

公开(公告)日：2024-07-25

申请号：US18172324

申请日：2023-02-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Chin-Sheng Wang ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/067 ,  H05K3/4679 ,  H05K2201/09454 ,  H05K2203/0789

Abstract: The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.

公开(公告)号：US20230240023A1

公开(公告)日：2023-07-27

申请号：US17684421

申请日：2022-03-02

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Chin-Sheng Wang ,  Guang-Hwa Ma ,  Tzyy-Jang Tseng

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/467 ,  H05K1/112 ,  H05K2201/0191

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

公开(公告)号：US11682658B2

公开(公告)日：2023-06-20

申请号：US17125981

申请日：2020-12-17

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Chia-Hao Chang ,  Tzu-Nien Lee

IPC: H01L25/075 ,  H01L33/54 ,  H01L33/62

CPC classification number: H01L25/0753 ,  H01L33/54 ,  H01L33/62 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A light-emitting package includes an encapsulating member, a plurality of light-emitting components disposed in the encapsulating member, a plurality of first electrode pads, a plurality of second electrode pads, and a plurality of conductive connection structures. The encapsulating member has a first surface and a second surface opposite to each other. Each light-emitting component has a light-emitting surface exposed on the first surface. Both the first electrode pads and the second electrode pads are exposed on the second surface. A first bonding surface of each first electrode pad and a second bonding surface of each second electrode pad are both flush with the second surface. The light-emitting components disposed on the first electrode pads are electrically connected to the first electrode pads. The conductive connection structures passing through the encapsulating member are electrically connected to the light-emitting components and the second electrode pads.

公开(公告)号：US11523503B2

公开(公告)日：2022-12-06

申请号：US17022128

申请日：2020-09-16

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Bo-Cheng Lin

IPC: H05K1/11 ,  H05K3/40

Abstract: A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.

公开(公告)号：US11445617B2

公开(公告)日：2022-09-13

申请号：US16379816

申请日：2019-04-10

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  John Hon-Shing Lau ,  Yu-Hua Chen ,  Tzyy-Jang Tseng

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/14 ,  H01L23/538

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

公开(公告)号：US20250149426A1

公开(公告)日：2025-05-08

申请号：US18895309

申请日：2024-09-24

Applicant: Unimicron Technology Corp.

Inventor： An-Sheng Lee ,  Chen-Hao Lin ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Chin-Sheng Wang ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16

Abstract: A package structure includes a package substrate, an organic interposer and an electronic unit. The package substrate includes a plurality of first pads. The organic interposer is disposed on the package substrate and includes a plurality of second pads. The second pads are directly connected to the first pads to electrically connected the organic interposer to the package substrate. At least one of each of the first pads and each of the second pads includes a pad portion and a plurality of contact portions connecting the pad portion. A first extension direction of the pad portion is different from a second extension direction of the contact portions. The electronic unit is disposed on the organic interposer, wherein the electronic unit is electrically connected to the package substrate through the organic interposer.