公开(公告)号：US07642545B2

公开(公告)日：2010-01-05

申请号：US10520886

申请日：2003-05-06

Applicant: Andrea Urban ,  Franz Laermer ,  Klaus Breitschwerdt

Inventor： Andrea Urban ,  Franz Laermer ,  Klaus Breitschwerdt

IPC: H01L21/00

CPC classification number: B81C1/00571 ,  B81B2203/033 ,  B81C2201/016 ,  H01L21/0332

Abstract: A layer system and a method for producing the layer system are provided, the layer system having a silicon layer, on which at least regionally a passivating layer is superficially deposited, the passivating layer having a first, at least largely inorganic partial layer and a second, at least largely polymer partial layer. The method includes producing on the silicon layer, a first, inorganic partial layer, and producing on this first partial layer a second, polymer partial layer, which form the passivating layer. The production of the intermediate layer occurs in such a way that the intermediate layer in its surface area adjoining the first partial layer is composed as the first partial layer, and the intermediate layer in its surface area adjoining the second partial layer is composed as the second partial layer. The composition of the intermediate layer transitions, either continuously or in steps, from the composition corresponding to the first partial layer into the composition corresponding to the second partial layer.

Abstract translation: 提供了一种用于制造层系统的层系统和方法，所述层系统具有硅层，其上至少区域地表面钝化钝化层，所述钝化层具有第一至少大部分无机部分层和第二层 ，至少主要是聚合物部分层。 该方法包括在硅层上制备第一无机部分层，并在该第一部分层上制备形成钝化层的第二聚合物部分层。 中间层的制造以与第一部分层相邻的表面区域的中间层构成为第一部分层的方式发生，并且与其邻接的第二部分层的表面区域中的中间层构成为第二部分层 部分层。 中间层的组成可以从对应于第一部分层的组合物连续地或逐步地转变成对应于第二部分层的组合物。

公开(公告)号：US07371601B2

公开(公告)日：2008-05-13

申请号：US11127457

申请日：2005-05-12

Applicant: David B. Rich ,  Steven M. Crist

Inventor： David B. Rich ,  Steven M. Crist

IPC: H01L21/00 ,  G01P15/00

CPC classification number: B81C1/00142 ,  B81B2201/0235 ,  B81B2201/032 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/016 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/0828

Abstract: A technique for manufacturing a piezoresistive sensing structure includes a number of process steps. Initially, a piezoresistive element is implanted into a first side of an assembly that includes a semiconductor material. A passivation layer is then formed on the first side of the assembly over the element. The passivation layer is then removed from selected areas on the first side of the assembly. A first mask is then provided on the passivation layer in a desired pattern. A beam, which includes the element, is then formed in the assembly over at least a portion of the assembly that is to provide a cavity. The passivation layer provides a second mask, in the formation of the beam, that determines a width of the formed beam.

Abstract translation: 制造压阻感测结构的技术包括多个工艺步骤。 最初，将压阻元件植入包括半导体材料的组件的第一侧。 然后在元件的组件的第一侧上形成钝化层。 然后从组件的第一侧上的选定区域去除钝化层。 然后以期望的图案在钝化层上提供第一掩模。 包括元件的梁然后在组件中形成在组件的至少一部分上以提供空腔。 钝化层在形成光束时提供第二掩模，其确定形成的光束的宽度。

公开(公告)号：US20060258038A1

公开(公告)日：2006-11-16

申请号：US11127457

申请日：2005-05-12

Applicant: David Rich ,  Steven Crist

Inventor： David Rich ,  Steven Crist

IPC: H01L21/00

CPC classification number: B81C1/00142 ,  B81B2201/0235 ,  B81B2201/032 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/016 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/0828

Abstract: A technique for manufacturing a piezoresistive sensing structure includes a number of process steps. Initially, a piezoresistive element is implanted into a first side of an assembly that includes a semiconductor material. A passivation layer is then formed on the first side of the assembly over the element. The passivation layer is then removed from selected areas on the first side of the assembly. A first mask is then provided on the passivation layer in a desired pattern. A beam, which includes the element, is then formed in the assembly over at least a portion of the assembly that is to provide a cavity. The passivation layer provides a second mask, in the formation of the beam, that determines a width of the formed beam.

Abstract translation: 制造压阻感测结构的技术包括多个工艺步骤。 最初，将压阻元件植入包括半导体材料的组件的第一侧。 然后在元件的组件的第一侧上形成钝化层。 然后从组件的第一侧上的选定区域去除钝化层。 然后以期望的图案在钝化层上提供第一掩模。 包括元件的梁然后在组件中形成在组件的至少一部分上以提供空腔。 钝化层在形成光束时提供第二掩模，其确定形成的光束的宽度。

公开(公告)号：US06967760B2

公开(公告)日：2005-11-22

申请号：US10703827

申请日：2003-11-07

Applicant: James A. Hunter

Inventor： James A. Hunter

IPC: G02B5/18 ,  G02B26/00 ,  G02B26/08 ,  G02F1/00 ,  G02F1/03 ,  G02F1/07 ,  G02F1/13 ,  G02F1/1368 ,  H01L21/00 ,  H01L21/28 ,  H01L21/302 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/423 ,  H01L29/49 ,  H01L31/153

CPC classification number: G02B26/0808 ,  B81B2201/045 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/016 ,  B81C2203/0735 ,  B81C2203/0778 ,  H01L27/0611

Abstract: An integrated device including one or more device drivers and a diffractive light modulator monolithically coupled to the one or more driver circuits. The one or more driver circuits are configured to process received control signals and to transmit the processed control signals to the diffractive light modulator. A method of fabricating the integrated device preferably comprises fabricating a front-end portion for each of a plurality of transistors, isolating the front-end portions of the plurality of transistors, fabricating a front-end portion of a diffractive light modulator, isolating the front end portion of the diffractive light modulator, fabricating interconnects for the plurality of transistors, applying an open array mask and wet etch to access the diffractive light modulator, and fabricating a back-end portion of the diffractive light modulator, thereby monolithically coupling the diffractive light modulator and the plurality of transistors.

Abstract translation: 包括一个或多个器件驱动器和单片耦合到所述一个或多个驱动器电路的衍射光调制器的集成器件。 一个或多个驱动器电路被配置为处理接收到的控制信号并将经处理的控制信号传送到衍射光调制器。 一种制造集成器件的方法优选包括制造用于多个晶体管中的每一个晶体管的前端部分，隔离多个晶体管的前端部分，制造衍射光调制器的前端部分，将前部 衍射光调制器的端部，制造用于多个晶体管的互连，施加开放阵列掩模和湿蚀刻以访问衍射光调制器，以及制造衍射光调制器的后端部分，从而将衍射光 调制器和多个晶体管。

公开(公告)号：US06666979B2

公开(公告)日：2003-12-23

申请号：US10046593

申请日：2001-10-29

Applicant: Jeffrey D. Chinn ,  Vidyut Gopal ,  Sofiane Soukane ,  Toi Yue Becky Leung

Inventor： Jeffrey D. Chinn ,  Vidyut Gopal ,  Sofiane Soukane ,  Toi Yue Becky Leung

IPC: H01L2100

CPC classification number: B81B3/0005 ,  B81B3/0008 ,  B81B2201/033 ,  B81C2201/016 ,  B81C2201/112

Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.

Abstract translation: 本发明涉及制造响应于刺激而自由移动的MEM内的表面的方法。 自由移动表面是在一系列步骤中制造的，其包括释放方法，其中通过牺牲层材料的无质子蚀刻来实现释放。 蚀刻步骤之后是清洁步骤，其中来自蚀刻步骤的副产物与可能导致静电的其它污染物一起被去除。 存在一系列蚀刻然后清洁步骤，使得执行这些步骤的许多“循环”。 在每个蚀刻步骤和每个清洁步骤之间，处理室压力通常突然降低，以产生湍流，并且有助于通过在降低腔室压力期间的泵送作用从结构表面和处理室排出的微粒去除。 最终的蚀刻/清洁循环之后可以是表面钝化步骤，其中清洁的表面被钝化和/或涂覆。

公开(公告)号：US20030080082A1

公开(公告)日：2003-05-01

申请号：US10046593

申请日：2001-10-29

Inventor： Jeffrey D. Chinn ,  Vidyut Gopal ,  Sofiane Soukane ,  Toi Yue Becky Leung

IPC: C23F001/00

CPC classification number: B81B3/0005 ,  B81B3/0008 ,  B81B2201/033 ,  B81C2201/016 ,  B81C2201/112

Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of nullcyclesnull of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.

公开(公告)号：US20020185469A1

公开(公告)日：2002-12-12

申请号：US10194167

申请日：2002-07-11

Applicant: Applied Materials, Inc.

Inventor： Dragan Podlesnik ,  Thorsten Lill ,  Jeff Chinn ,  Shaoher X. Pan ,  Anisul Khan ,  Maocheng Li ,  Yiqiong Wang

IPC: C23F001/00 ,  B44C001/22 ,  C03C015/00 ,  C03C025/68

CPC classification number: H01L27/1087 ,  B81B2201/052 ,  B81B2203/0315 ,  B81B2203/033 ,  B81C1/00119 ,  B81C2201/016 ,  H01L21/3065 ,  H01L21/3086

Abstract: The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.

Abstract translation: 本公开涉及我们发现用于蚀刻衬底中的多部分空腔的特别有效的方法。 该方法提供了首先蚀刻成形开口，在成形开口的内表面的至少一部分上沉积保护层，然后直接在成形开口下面蚀刻成形腔，并与成形开口连续连通。 保护层在蚀刻成形腔体期间保护成形开口的蚀刻轮廓，从而如果需要，成形开口和成形腔体可以被蚀刻以具有不同的形状。 在本发明方法的特定实施例中，横向蚀刻阻挡层和/或注入的蚀刻停止点也用于引导蚀刻工艺。 本发明的方法可以应用于需要或期望提供具有不同形状的成形开口和下面的成形腔的任何应用。 只要需要对成形开口的尺寸进行严格控制，该方法也是有用的。

公开(公告)号：WO2016191063A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/030818

申请日：2016-05-04

Applicant: SNAPTRACK, INC. ,  SHARP CORPORATION, SHARP KABUSHIKI

Inventor： SASAGAWA, Teruo ,  CHAE, Junghun ,  STEYN, Jasper Lodewyk ,  HARA, Takeshi ,  YAMATO, Asahi

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00698 ,  B81B3/0086 ,  B81B2203/0163 ,  B81B2207/053 ,  B81C2201/016 ,  B81C2201/0181

Abstract: This disclosure provides systems, methods and apparatus including devices that include layers of passivation material covering at least a portion of an exterior surface of a thin film component within a microelectromechanical device. The thin film component may include an electrically conductive layer that connects via an anchor to a conductive surface on a substrate. The disclosure further provides processes for providing a first layer of passivation material on an exterior surface of a thin film component and for electrically connecting that thin film component to a conductive surface on a substrate. The disclosure further provides processes for providing a second layer of passivation material on any exposed surfaces of the thin film component after release of the microelectromechanical device.

Abstract translation: 本公开提供了包括装置的系统，方法和装置，其包括覆盖微机电装置内的薄膜部件的外表面的至少一部分的钝化材料层。 薄膜部件可以包括通过锚固件连接到基板上的导电表面的导电层。 本公开还提供了在薄膜部件的外表面上提供第一钝化材料层并将该薄膜部件电连接到基板上的导电表面的工艺。 本公开还提供了在释放微机电装置之后在薄膜组件的任何暴露表面上提供第二钝化材料层的工艺。

公开(公告)号：WO2007147137A2

公开(公告)日：2007-12-21

申请号：PCT/US2007/071378

申请日：2007-06-15

Applicant: SITIME CORPORATION ,  GUPTA, Pavan ,  RAZDA, Eric

Inventor： GUPTA, Pavan ,  RAZDA, Eric

IPC: H01L23/52

CPC classification number: B81B7/0083 ,  B81B7/007 ,  B81B7/0077 ,  B81B2201/0271 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00333 ,  B81C1/00341 ,  B81C2201/016 ,  B81C2203/0118 ,  B81C2203/0154 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/498 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A stacked die package for an electromechanical resonator system includes a chip that contains an electromechanical resonator bonded onto the control chip for the electromechanical resonator by a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system (NEMS) resonator. Packaging configurations that may include the chip that contains the electromechanical resonator and the control chip include chip-on-lead (COL), chip-on-paddle (COP), and chip-on-tape (COT) packages. The stacked die package provides small package footprint and/or low package thickness, as well as low thermal resistance and a robust conductive path between the chip that contains the electromechanical resonator and the control chip.

Abstract translation: 用于机电谐振器系统的堆叠管芯封装包括芯片，其包含通过热和/或导电环氧树脂粘合到用于机电谐振器的控制芯片上的机电谐振器。 在各种实施例中，机电谐振器可以是微机电系统（MEMS）谐振器或纳米机电系统（NEMS）谐振器。 可以包括包含机电谐振器和控制芯片的芯片的封装结构包括芯片引线（COL），片上芯片（COP）和片上芯片（COT）封装。 堆叠管芯封装提供小的封装封装和/或低封装厚度，以及低热阻和在包含机电谐振器的芯片和控制芯片之间的坚固的导电路径。

公开(公告)号：WO2003103022A1

公开(公告)日：2003-12-11

申请号：PCT/US2003/015475

申请日：2003-05-14

Applicant: SILICON LIGHT MACHINES

Inventor： HUNTER, James, A.

IPC: H01L21/00

CPC classification number: G02B26/0808 ,  B81B2201/045 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/016 ,  B81C2203/0735 ,  B81C2203/0778 ,  H01L27/0611

Abstract: An integrated device including one or more device drivers and a diffractive light modulator monolithically coupled to the one or more driver circuits. The one or more driver circuits are configured to process received control signals and to transmit the processed control signals to the diffractive light modulator. A method of fabricating the integrated device preferably comprises fabricating a front-end portion for each of a plurality of transistors, isolating the front-end portions of the plurality of transistors, fabricating a front-end portion of a diffractive light modulator, isolating the front-end portion of the diffractive light modulator, fabricating interconnects for the plurality of transistors, applying an open array mask and wet etch to access the diffractive light modulator, and fabricating a back-end portion of the diffractive light modulator, thereby monolithically coupling the diffractive light modulator and the plurality of transistors.

Abstract translation: 包括一个或多个器件驱动器和单片耦合到所述一个或多个驱动器电路的衍射光调制器的集成器件。 一个或多个驱动器电路被配置为处理接收到的控制信号并将经处理的控制信号传送到衍射光调制器。 一种制造集成器件的方法优选包括制造用于多个晶体管中的每一个晶体管的前端部分，隔离多个晶体管的前端部分，制造衍射光调制器的前端部分，将前部 衍射光调制器的前端部分，制造用于多个晶体管的互连，施加开放阵列掩模和湿蚀刻以访问衍射光调制器，以及制造衍射光调制器的后端部分，从而将衍射光 光调制器和多个晶体管。