公开(公告)号：US20250015795A1

公开(公告)日：2025-01-09

申请号：US18750277

申请日：2024-06-21

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Atul DWIVEDI

IPC: H03K17/14 ,  H03K17/30 ,  H03K17/60

Abstract: An integrated circuit comprises a current source, a plurality of parallel transistors, a plurality of switches, switch control circuitry, and measurement circuitry. Each switch selectively couples the current source to a corresponding transistor. The switch control circuitry is configured to, at different times, cause all the switches to close and, separately for each transistor, cause the switch associated with each transistor to close while causing all other switches to open. The measurement circuitry is configured to measure, separately for each of the transistors, a base-emitter voltage (VBE) when all the switches are closed and a VBE when only the switch associated with each transistor is closed, determine a ΔVBE for each of the plurality of transistors by calculating a difference between the VBE when only the switch associated with each transistor is closed and the VBE when all the switches are closed, and calculate an average of all the ΔVBEs.

公开(公告)号：US20250007526A1

公开(公告)日：2025-01-02

申请号：US18345298

申请日：2023-06-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  UNVERSITE DE BORDEAUX

Inventor： Denis Michael FLORES PAZOS ,  Andreia CATHELIN ,  Yann DEVAL

IPC: H03L7/18 ,  H03L7/099

Abstract: In various embodiments, a frequency dividing circuit is provided. The frequency dividing circuit may include a first circuit including an m-bit multiplexer configured to receive a positive binary word and a negative binary word as inputs. The frequency dividing circuit may receive a controlled oscillator output signal and a complement of the controlled oscillator output signal, generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word. A ratio of the frequency dividing circuit output signal frequency to the controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.

公开(公告)号：US20250007463A1

公开(公告)日：2025-01-02

申请号：US18751595

申请日：2024-06-24

Applicant: STMicroelectronics International N.V.

Inventor： Raffaele Enrico FURCERI ,  Marco ZAMPROGNO

IPC: H03D3/00 ,  H03D7/16

Abstract: Faults in a periodically oscillating MEMS mass are detected by processing a position signal, having an amplitude and oscillation frequency, generated as a function of mass position. First and second reference signals formed by samples of quadrature sinusoids at the oscillation frequency are generated. First and second multipliers generate a first product signal and a second product signal, respectively, via multiplication of the position signal by the first and second reference signals. The first and second product signals are low pass filtered to generate first and second filtered signals, respectively. An estimator circuit determines estimates of the amplitude as a function of the first and second filtered signals. A decision circuit detects the presence of faults on the basis of a comparison of the estimates with a range of values.

公开(公告)号：US20250006267A1

公开(公告)日：2025-01-02

申请号：US18753094

申请日：2024-06-25

Applicant: STMicroelectronics International N.V.

Inventor： Radouane Habhab ,  Vincenzo Della Marca ,  Nadia Miridi ép Seroschtanoff ,  Pascal Masson ,  Franck Melul ,  Madjid Akbal

IPC: G11C16/10 ,  H01L29/423 ,  H10B43/27

Abstract: The non-volatile memory device includes memory cells including a control gate vertically buried in a semiconductor substrate doped with a first type of dopant and a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate. The device furthermore includes a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.

公开(公告)号：US20250002333A1

公开(公告)日：2025-01-02

申请号：US18215322

申请日：2023-06-28

Applicant: STMicroelectronics International N.V.

Inventor： Eric SAUGIER

IPC: B81C1/00 ,  B81B7/02

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. The silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. The silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. After emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. The thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.

公开(公告)号：US20240429286A1

公开(公告)日：2024-12-26

申请号：US18341147

申请日：2023-06-26

Applicant: STMicroelectronics International N.V.

Inventor： Simone RASCUNA ,  Paolo BADALA ,  Gabriele BELLOCCHI ,  Valeria PUGLISI ,  Dario TENAGLIA

IPC: H01L29/16 ,  H01L29/40 ,  H01L29/45 ,  H01L29/47

Abstract: Various embodiments of the present disclosure disclose improved silicon carbide (SiC) power devices and methods of fabrication of such devices. A SiC power device includes a semiconductor base material with a first side and a second side and a first metallic layer disposed on the first side of the semiconductor base material that forms ohmic contacts and Schottky contacts. The SiC power device may be fabricated by forming a first metallic layer on a first side of a semiconductor base material to form a Schottky contact, forming a second metallic layer over the first metallic layer to form a reflective barrier covering the Schottky contact, removing one or more portions of the second metallic layer to expose a first portion of the first metallic layer, and forming silicide portions on the first metallic layer to form ohmic contacts within the Schottky contact.

公开(公告)号：US20240429232A1

公开(公告)日：2024-12-26

申请号：US18747571

申请日：2024-06-19

Applicant: STMicroelectronics International N.V.

Inventor： Abderrezak MARZAKI ,  Alexandre VILLARET

IPC: H01L27/06 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit includes a substrate having a front face. A capacitive element includes, over a surface at the front face, a stack made of: a first conductive armature, a dielectric interface region over the first conductive armature, and a second conductive armature over the dielectric interface region. The first conductive armature includes a gate metal layer located over a layer of a material with a high dielectric constant.

公开(公告)号：US20240427514A1

公开(公告)日：2024-12-26

申请号：US18337751

申请日：2023-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Urmishkumar Karsanbhai Patel ,  Danish Hasan Syed ,  Prateek Singh

IPC: G06F3/06

Abstract: According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.

公开(公告)号：US20240427408A1

公开(公告)日：2024-12-26

申请号：US18670083

申请日：2024-05-21

Applicant: STMicroelectronics International N.V

Inventor： Stephane Le Coq

IPC: G06F1/3234 ,  G06F1/3287

Abstract: The present disclosure relates to a method for managing the deep sleep mode of an embedded system. In embodiments, the method includes determining a value of the electrical charge used, during a deep sleep mode of the system, for saving software-context data into a non-volatile memory of the system; determining a value of a current used, during a deep sleep mode of the system, for saving software-context data into a volatile memory of the system; determining, from the previously determined values, a threshold value defining a duration beyond which a power consumption caused by saving software-context data into the non-volatile memory is less than that into the volatile memory; saving the software-context data into the non-volatile or volatile memory according to the expected duration of deep sleep mode of the system.

公开(公告)号：US20240425352A1

公开(公告)日：2024-12-26

申请号：US18741058

申请日：2024-06-12

Applicant: STMicroelectronics International N.V.

Inventor： Luca SEGHIZZI ,  Federico VERCESI ,  Gianluca LONGONI ,  Andrea NOMELLINI

IPC: B81B3/00 ,  G01P15/125

Abstract: An inertial MEMS device includes an inertial element provided by a movable structure that is responsive to movement. The moveable structure is formed in a first structural layer of semiconductor material. A suspended structure extends above the movable structure at a distance therefrom. The suspended structure is formed in a second structural layer of semiconductor material and carries a piezoelectric structure. The suspended structure and the piezoelectric structure form a wake-up element that generates an activation signal in presence of vibrations or shocks. The inertial element and the wake-up element are contained in a chamber formed by a substrate and a cap, together with peripheral portions of the first and the second structural layers.