Abstract:
Universal switched power converter having a transformer that comprises a first winding (11-3) divided into two parts and having an intermediate tap (11-3-1), and a second winding (11-9) connected in cascade with rectifier means (12) and filter means (13), so that a first current flows through the part of said first winding (11-3) comprised between the end of the primary winding (11-3) connected to a first input terminal (11-1) and the intermediate tap (11-3-1) and through a second switching element (11-6) connected to the intermediate tap (11-3-1) and to a second input terminal (11-2), when the input voltage applied across the input terminals (11-1, 11-2) is close to a first predetermined voltage value and the second switching element (11-6) is in a conducting state.
Abstract:
A self-regulated synchronous rectifier is connected between a secondary transformer winding and an LC filter. The rectifier includes two MOSFETs each having a gate connected in series with a gate protection circuit. Each gate protection circuit includes a divider bridge and a switch connected in parallel with the divider bridge and having an open position and a closed position and the rectifier includes a control device for controlling the switches which receives an input signal proportional to the input voltage of the rectifier and produces output signals for controlling the switches.
Abstract:
The invention comes within the branch of data transmission comprising the multiplexing of k digital unitary trains of rhythms substantially equal into a single digital train having a rhythm substantially k times faster than the unitary trains and the reverse demultiplexing. It concerns a device enabling the checking of multiplexing/demultiplexing operations by comparison between a word having a determined length sampled in a (slow) unitary train and a word having the same length sampled in the (rapid) multiplexed train.
Abstract:
The invention concerns the determining of the length of a repetitive digital train of unknown length, whose synchronization is ensured by a single synchronization bit. That search is effected automatically by a logic circuit which detects the existence of a fixed bit subsequent to a repetitive scanning operation in which the supposed length of the train is increased by one unit each time. To decide whether the result is surely positive, the passing of the train must be repeated a fairly great number of times. To save time, a conclusion of NO is obtained on a smaller number of passes of the train.
Abstract:
Equipment for detecting, on the basis of two consecutive tests, the existence of one or several telegraph channels on one or several telephone channels of a frequency multiplex system. The first test, which is relatively fast, is based on the presence of a predetermined frequency in the channel. The second test, which is slower in operation, is based on the amplitude identity of two moments, formed by alternate transitions in the transmission signal.