公开(公告)号：EP0766295A1

公开(公告)日：1997-04-02

申请号：EP95830404.0

申请日：1995-09-29

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Zambrano, Raffaele

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L21/26586 ,  H01L29/1004 ,  H01L29/732

Abstract: A process for forming a structure of a high-frequency bipolar transistor on a layer (3) of a semiconductor material with conductivity of a first type, is of the type which comprises the step of forming a first shallow base region (17) by implantation along a selected direction of implantation and using a dopant with a second type of conductivity, which region extends from a first surface (6) of the semiconductor material layer (3) and encloses, toward said first surface (6), an emitter region (24) with conductivity of the first type. In accordance with the invention, the implantation step includes at least one process phase at which the direction of implantation is maintained at a predetermined angle (x) significantly greater than zero degrees from the direction of a normal line (N) to said first surface (6). Preferably, the implantation angle (x) is of about 45 degrees.

Abstract translation: 在第一类电导率的半导体材料的层（3）上形成高频双极晶体管的结构的方法是包括通过注入形成第一浅基极区（17）的步骤的方法 沿着所选择的注入方向并使用具有第二类型导电性的掺杂剂，该区域从半导体材料层（3）的第一表面（6）延伸并包围所述第一表面（6），发射极区域 24）具有第一类型的电导率。 根据本发明，植入步骤包括至少一个工艺阶段，在该工艺阶段，将植入方向保持在从法线（N）的方向到所述第一表面（N）显着大于零度的预定角度（x） 6）。 优选地，注入角度（x）约为45度。

公开(公告)号：EP0763887A1

公开(公告)日：1997-03-19

申请号：EP95830377.8

申请日：1995-09-14

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruccoleri, Melchiorre ,  Demicheli, Davide ,  Demicheli, Marco ,  Patti, Giuseppe

IPC: H03G1/00 ,  H03G3/20 ,  G11B5/02

CPC classification number: H03G3/3026 ,  G11B5/02 ,  H03G1/0088

Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators.
The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

Abstract translation: 所描述的电路包括连接到差分放大器（VGA）的输出的双半波整流器（DHWR），以便产生取决于放大器（VGA）的输出信号的半波幅度的两个量， 每个具有连接到整流器（DHWR）的输出（OUT1，OUT2）和参考输入（IN-1，IN-2）的输入（IN + 1，IN + 2））的两个比较器（COMP1，COMP2） 当各个半波的振幅大于施加到参考输入（IN-1，IN-2）的电平时，产生相应的输出信号，并且处理装置（Str1，A1，R1，Str2，A2，R2， C），用于根据两个比较器的输出信号的持续时间产生用于调节放大器的增益的信号。 当待放大的信号（v +，v-）不对称时，可以有利地使用该电路。

公开(公告)号：EP0639894B1

公开(公告)日：1997-02-12

申请号：EP93830354.2

申请日：1993-08-18

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Aiello, Natale ,  Palara, Sergio ,  Scaccianoce, Salvatore

IPC: H03K17/08 ,  H03K17/16

CPC classification number: H03K17/08126 ,  H03K17/0826 ,  H03K17/16

公开(公告)号：EP0740261A1

公开(公告)日：1996-10-30

申请号：EP95830171.5

申请日：1995-04-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruno, Dario ,  Poluzzi, Rinaldo ,  Manaresi, Nicolo ,  Franchi, Eleonora

IPC: G06G7/60 ,  G05F3/24

CPC classification number: G06N7/043 ,  G05F3/24

Abstract: The analog processor of this invention is programmable and capable of storing the processing coefficients in analog form.
It comprises a storage section (MEM) having at least one output, plural outputs in most cases, and being adapted to respectively generate programming signals (PP) on such outputs; the storage section (MEM) is input a plurality of supply voltage signals (VI) and is operative to produce, in connection with information stored therein, one of the supply voltage signals on each of the outputs, it being understood that one voltage signal may be produced on several such outputs.
Advantageously, the processor can also be programmed in a simple manner from circuits of the digital type if switches (SW) controlled by storage elements (E) are used in the storage section (MEM).

Abstract translation: 本发明的模拟处理器是可编程的并且能够以模拟形式存储处理系数。 它包括具有至少一个输出的存储部分（MEM），在大多数情况下多个输出，并且适于在这种输出上分别产生编程信号（PP）; 存储部分（MEM）输入多个电源电压信号（VI），并且可操作地结合存储在其中的信息产生每个输出上的电源电压信号中的一个，应当理解，一个电压信号可以 在几个这样的产出上产生。 有利地，如果在存储部分（MEM）中使用由存储元件（E）控制的开关（SW）），则处理器也可以以简单的方式从数字类型的电路编程。

公开(公告)号：EP0735677A1

公开(公告)日：1996-10-02

申请号：EP95830123.6

申请日：1995-03-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pulvirenti, Francesco ,  Ursino, Riccardo ,  Gariboldi, Roberto

IPC: H03K3/011 ,  H03K3/0231

CPC classification number: H03K3/011 ,  H03K3/0231 ,  H03K3/354

Abstract: The oscillating circuit in accordance with the present invention comprises a capacitor C, a charge circuitry CCA and a control circuitry CCO. The charge circuitry CCA includes a first GEN1 and a second GEN2 current generators having respectively a first and a second current values and opposite directions and switching means SW1,SW2 designed to couple alternatively the generators GEN1,GEN2 to the capacitor C. The control circuitry CCO has a voltage input coupled to the capacitor C and an output coupled to control inputs of the switching means SW1,SW2 and includes a comparator with hysteresis having a lower threshold and an upper threshold.
If for the difference between the upper threshold and the lower threshold a value is chosen essentially proportional to the ratio of the product to the sum of the two current values the oscillation frequency and the duty cycle depend neither on the supply voltage nor the temperature nor the process.

Abstract translation: 根据本发明的振荡电路包括电容器C，充电电路CCA和控制电路CCO。 充电电路CCA包括分别具有第一和第二电流值和相反方向的第一GEN1和第二GEN2电流发生器，以及设计成将发电机GEN1，GEN2交替耦合到电容器C的开关装置SW1，SW2。控制电路CCO 具有耦合到电容器C的电压输入和耦合到开关装置SW1，SW2的控制输入的输出，并且包括具有较低阈值和较高阈值的滞后的比较器。 如果对于上限阈值和下限阈值之间的差异，则选择一个值基本上与产品与两个电流值之和的比例成比例，振荡频率和占空比既不依赖于电源电压也不依赖于温度， 处理。

公开(公告)号：EP0735580A1

公开(公告)日：1996-10-02

申请号：EP95830125.1

申请日：1995-03-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Zambrano, Raffaele

IPC: H01L21/762 ,  H01L21/763

CPC classification number: H01L21/763 ,  H01L21/76232

Abstract: A novel process for forming, on a semiconductor substrate, a dielectric isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of:

defining an isolation region (45) on a layer of silicon oxide (42) overlying a silicon layer (41);
selectively etching the silicon (41) to provide the isolation region (45);
growing thermal oxide (43) over the interior surfaces of the isolation structure (45);
depositing dielectric (46) conformingly; and
oxidizing the deposited dielectric (46).

Abstract translation: 一种用于在半导体衬底上形成集成电路的两个区域之间的介电隔离结构的新颖方法，其中已经定义了与其集成的电子元件的有源区域包括以下步骤：在层上限定隔离区域（45） 覆盖硅层（41）的氧化硅（42）; 选择性地蚀刻硅（41）以提供隔离区（45）; 在隔离结构（45）的内表面上生长热氧化物（43）; 沉积电介质（46）; 和氧化沉积的电介质（46）。

公开(公告)号：EP0720078A1

公开(公告)日：1996-07-03

申请号：EP94830593.3

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Franchi, Eleonora

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises:

a) at least one first (M1) and one second (M2) transistor of the same type having respectively two control terminals (G1,G2) and having essentially the same threshold with the control terminal (G1) of said first transistor (M1) connected to a constant potential node (IT),
b) a current mirror (MC) having at least one input terminal (IM) and one output terminal (OM) coupled respectively to said first (M1) and second (M2) transistors so as to supply to them the bias currents,
c) a first (VDD) and a second (GND) potential reference, and
d) a voltage divider (VD) having an intermediate tap (E3) and a first (E1) and a second (E2) end terminals.

The control terminal (G2) of said second transistor (M2) is coupled to said tap (E3) and said divider (VD) is biased by coupling said first (E1) and second (E2) end terminals respectively to said first (VDD) and second (GND) potential references.
The output (OT) is coupled to one (E1) of said end terminals.

Abstract translation: 根据本发明的晶体管阈值提取电路具有输出（OT），包括：a）相同类型的至少一个第一（M1）和一个第二（M2）晶体管分别具有两个控制端（G1，G2） 并且具有与连接到恒定电位节点（IT）的所述第一晶体管（M1）的控制端子（G1）基本相同的阈值，b）具有至少一个输入端子（IM）和一个输出端的电流镜 端子（OM）分别耦合到所述第一（M1）和第二（M2）晶体管，以便向它们提供偏置电流，c）第一（VDD）和第二（GND）电位参考，以及d）分压器 （VD）具有中间抽头（E3）和第一（E1）和第二（E2）端子端子。 所述第二晶体管（M2）的控制端（G2）耦合到所述抽头（E3），并且所述分压器（VD）分别通过将所述第一（E1）和第二（E2）端子端分别耦合到所述第一（VDD） 和第二（GND）电位参考。 输出（OT）耦合到所述端子的一个（E1）。

公开(公告)号：EP0687066A1

公开(公告)日：1995-12-13

申请号：EP94830284.9

申请日：1994-06-10

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bontempo, Gregorio ,  Pulvirenti, Francesco ,  Colletti, Paolo ,  Gariboldi, Roberto

IPC: H03K17/082

CPC classification number: H03K17/284 ,  H03K17/0822

Abstract: The invention relates to a non-dissipative device for protecting against overloading an integrated circuit having multiple independent channels, being of the type which comprises an input terminal (IN) and an output terminal (OUT) having an integrated switch (1) connected therebetween which consists of a first or input portion (2), a logic gate (PL1) with two inputs (I3,I4) a second or control portion (3), and a third or output portion (4), all in series with one another. The device further comprises a circuit (A) for generating the on- and off-times (Ton,Toff) of the integrated switch (1) connected between an output (O4) of the third portion (4) and an input terminal (I4) of said logic gate (PL1).

Abstract translation: 本发明涉及一种非消散装置，用于防止具有多个独立通道的集成电路的过载，该集成电路具有包括输入端（IN）和输出端（OUT）的类型，该输出端（IN）和输出端（OUT）之间连接有集成开关（1） 由第一或输入部分（2），具有两个输入（I3，I4），第二或控制部分（3）的逻辑门（PL1），以及彼此串联的第三或输出部分（4） 。 该装置还包括用于产生连接在第三部分（4）的输出（O4）和输入端（I4）之间的集成开关（1）的开和关时间（Ton，Toff）的电路（A） ）的逻辑门（PL1）。

公开(公告)号：EP0684550A1

公开(公告)日：1995-11-29

申请号：EP94830241.9

申请日：1994-05-23

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Matranga, Vincenzo ,  Giacalone, Biagio ,  Abruzzese, Massimo

IPC: G06F7/60

CPC classification number: G06N7/04

Abstract: Method of parallel processing of multiple inference rules (R) organised in fuzzy sets or logical functions of multiple fuzzy sets comprising membership functions (I') defined in a so-called universe of discourse (U) and said inference rules (R) being configured essentially as IF-THEN rules with at least one antecedent preposition and at least one consequent implication and each preposition comprising at least one term (T) of comparison between membership functions (I') and a plurality of input data (I) and each term (T) being separated by logical operators (OL).
The method associates with the logical operators (OL) maximum and minimum operations among two or more elements and calculates exhaustively the overall degree of truth (Ω) of a rule (R) with a maximum or minimum of N partial truth levels (w).

Abstract translation: 在模糊集合或多个模糊集包含在话语中（U）和所述推理规则（R）的一个所谓的宇宙定义隶属函数（I“）的逻辑功能组织的多个推理规则（R）的并行处理方法被配置 基本上如IF-THEN与至少一个先行介词和至少一个随后的含义，并且每个介词包括隶属函数之间的比较中的至少一个术语（T）（I“）和输入数据（I）的多元的，每个术语的规则 （T）通过逻辑运算符（OL）分离。 一个规则（R）与N-局部真理水平的最大值或最小值（W）的与逻辑运算符（OL）的最大值和两个或多个元件，并且计算详尽之间最小限度的操作的方法相关联的真理（OMEGA）的整体程度。

公开(公告)号：EP0632484A1

公开(公告)日：1995-01-04

申请号：EP93830283.3

申请日：1993-06-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Grasso, Antonio ,  Pinto, Antonio

IPC: H01L21/00 ,  B23K20/00

CPC classification number: H01L24/85 ,  B23K20/005 ,  B23K2201/40 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/78302 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method for connecting wire leads (7) between a semiconductor circuit chip (1) and corresponding terminal connectors comprises the steps of,

providing a bonding tool (9) having a working end (12) formed with at least a pair of grooves (13,14) of different length,
holding one end of the wire (7) on the pin in one (13) of said grooves and bonding it, and
holding the other end of said wire on the chip (1) in the other (14) of said grooves and bonding it. The grooves (13,14) have different lengths to allow of different wire spans across the bonded connection areas, on the chip and the pins.

Abstract translation: （12）形成有至少一对凹槽的一种半导体电路芯片之间的连接引线（7）的方法（1）和对应的端子连接器包括以下步骤，提供（9）具有工作端部的接合工具（13 ，14）的不同长度的，（在销上7）（在一个（13）保持所述金属丝的一个端部，所述槽的和结合它，并且保持所述金属丝的另一端在另一方的芯片1）（14 ）的所述槽和结合它。 槽（13,14）具有不同的长度，以允许不同的导线的整个键合连接区域跨越，所述芯片和所述管脚上。