公开(公告)号：JPH11317532A

公开(公告)日：1999-11-16

申请号：JP31830498

申请日：1998-10-22

Applicant: ST MICROELECTRONICS SA

Inventor： DUCLOS FRANCK

IPC: G11B5/40 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L27/04 ,  H01L27/08 ,  H01L29/861 ,  H05F3/02

Abstract: PROBLEM TO BE SOLVED: To obtain a protective device of a structure, wherein the device has a low electrostatic capacity for protection against electrostatic discharge(ESD), the manufacture of the device is executed in the form of a monolithic silicon chip, and the device is formed of an assembly of a constitution, wherein two groups of diodes connected in series are arranged in parallel to each other. SOLUTION: This assembly is of a constitution, for which two groups of diodes of a first group comprising a second diode D2 and a first diode D1, arranged in series with the diode D2 and a second group comprising a fourth diode D4 and a third diode D3 arranged in series with the diode D4 are provided within a first conductivity type semiconductor substrate 20 and the two groups of the diodes are arranged in parallel to each other. Each of the first and third diodes D1 and D3 in this assembly comprises other conductivity type adjacent regions, which are lightly doped with the second conductivity-type impurities and are formed into an isolated well, each of the second and fourth diodes D2 and D4 in the assembly comprises the other conductivity-type regions, separated from each other and metal materials M1 to M4 are connected with diode electrodes for forming parallel assemblies in a desirable series.

公开(公告)号：JP2014002382A

公开(公告)日：2014-01-09

申请号：JP2013124906

申请日：2013-06-13

Applicant: St Microelectronics Sa ,  エス テ マイクロエレクトロニクス エス アー ,  Commissariat A L'energie Atomique Et Aux Energies Alternatives ,  コミサリア ア エナジー アトミック エ オックス エナジーズ オルタネティヴ

Inventor： MICHEL MARTY ,  FLAVIEN HIRIGOYEN ,  JOSEP SEGURA PUCHADES ,  HELENE WEHBE-ALAUSE ,  UMBERTO ROSSINI

IPC: G02F1/1368 ,  H01L29/786

CPC classification number: G02F1/1368 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136277 ,  G02F2001/136281 ,  H01L33/36

Abstract: PROBLEM TO BE SOLVED: To provide a panel in which MOS control transistors are protected from light.SOLUTION: In the panel formed by arrayed cells and allowed to be used for a nano projector, each cell has a liquid crystal layer surrounded by an upper side transparent electrode and a lower side transparent electrode, a MOS control transistor is arranged on the upper side of the upper side transparent electrode and each MOS control transistor is coated with at least three metal coating layers. The MOS control transistors of respective cells are arranged on the corner parts of the respective cells so that the MOS control transistors of an aggregate consisting of four adjacent cells are arranged on the center part of the aggregate. The upper metal coating layer coats the upper side of the MOS control transistors of the aggregate of the four adjacent cells. The panel comprises a first conductive annular body surrounding the MOS control transistors in each aggregate of four adjacent cells, and the first annular body extends from the lower metal coating layer to the upper side transparent electrodes of respective cells through an insulator.

Abstract translation: 要解决的问题：提供一种面板，其中MOS控制晶体管被保护免受光照。解决方案：在由阵列单元形成并允许用于纳米投影仪的面板中，每个单元具有由上侧包围的液晶层 透明电极和下侧透明电极，在上侧透明电极的上侧设置MOS控制晶体管，并且每个MOS控制晶体管被涂覆有至少三个金属涂层。 各个单元的MOS控制晶体管被布置在各个单元的角部，使得由四个相邻单元组成的集合体的MOS控制晶体管布置在聚集体的中心部分。 上金属涂层覆盖四个相邻单元的集合体的MOS控制晶体管的上侧。 面板包括围绕四个相邻单元的每个聚集体中的MOS控制晶体管的第一导电环形体，并且第一环形体通过绝缘体从下金属涂层延伸到相应单元的上侧透明电极。

公开(公告)号：JP2008065843A

公开(公告)日：2008-03-21

申请号：JP2007259733

申请日：2007-10-03

Applicant: St Microelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： WUIDART SYLVIE

IPC: G06F1/04 ,  G06K19/07 ,  G06F1/06 ,  G06F1/08 ,  G06F21/06 ,  G06K17/00 ,  G06K19/073

CPC classification number: G06K19/073 ,  G06F1/08 ,  G06K19/07363

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit capable of using an external clock signal or random clock signal as an internal synchronizing signal. SOLUTION: The integrated circuit (1) which receives the external clock signal (CK-ext) is controlled in clocking internally and the random clock signal (CK-al) which is generated internally is used additionally. With a binary switching command K corresponding to an instruction to be executed, one of those clock signals (CK-ext and CK-al) is used as a base for clock generation and an internal clock signal (CK-in) is obtained according to the one of them. The random clock signal (CK-al) is preferably used as the base for operation for processing at least secret data. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供能够使用外部时钟信号或随机时钟信号作为内部同步信号的集成电路。

解决方案：接收外部时钟信号（CK-ext）的集成电路（1）在内部进行时钟控制，另外使用内部生成的随机时钟信号（CK-a1）。 使用与要执行的指令对应的二进制切换命令K，将这些时钟信号（CK-ext和CK-a1）中的一个用作时钟产生的基准，并且根据以下情况获得内部时钟信号（CK-in） 其中之一。 随机时钟信号（CK-a1）优选地用作用于至少处理秘密数据的操作的基础。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007074727A

公开(公告)日：2007-03-22

申请号：JP2006239571

申请日：2006-09-04

Applicant: Commissariat A L'energie Atomique ,  St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー ,  コミッサリア ア レネルジ アトミックCommissariat A L’Energie Atomique

Inventor： BOUCHE GUILLAUME ,  PARAT GUY

IPC: H03H9/17 ,  H01L41/09 ,  H01L41/187 ,  H01L41/22 ,  H03H3/02

CPC classification number: H03H9/172 ,  H03H3/02 ,  H03H9/0547

Abstract: PROBLEM TO BE SOLVED: To provide an acoustic resonator which is connected to a support of an integrated circuit, of which an architecture has minimum coarseness, and which can be made into thin film formation step of adjusting a resonant frequency. SOLUTION: The integrated circuit includes at least one interconnection level and an acoustic resonator provided with a support comprising at least one bilayer assembly comprising a layer of high acoustic impedance material and a layer of low acoustic impedance material, and an active element. The support further has a protruding element arranged on a metallization level of the interconnection level, thereby making it possible to produce an electrical contact between the interconnection level and the active element of the acoustic resonator. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种连接到集成电路的支撑件的声谐振器，其结构具有最小的粗糙度，并且可以制成调整谐振频率的薄膜形成步骤。 解决方案：集成电路包括至少一个互连级别和声学谐振器，该谐振器设置有包括至少一个双层组件的支撑件，该组合件包括高声阻抗材料层和低声阻抗材料层以及有源元件。 支撑件还具有布置在互连电平的金属化水平上的突出元件，从而使得可以在互连电平和声谐振器的有源元件之间产生电接触。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005071380A

公开(公告)日：2005-03-17

申请号：JP2004248342

申请日：2004-08-27

Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

Inventor： PISTOULET PIERRE

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/14 ,  G06F21/02

CPC classification number: G06F12/1425 ,  G06F12/0875 ,  Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To provide an access controller with a simple structure allowing reduction of peak power consumption. SOLUTION: This access controller controlling access to a data memory has: a means storing a plurality of attributes (ATi) for defining a right of the access to the data memory (DMEM); cache memories (CMEM, CMC) storing a prescribed number of attributes; and a synchronous attribute retrieval circuit (ASC2) retrieving the attribute inside the storage means (DMEM, ATMEM) when the attribute is absent inside the cache memory. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有简单结构的访问控制器，从而降低峰值功耗。 控制对数据存储器的访问的该访问控制器具有：存储用于定义访问数据存储器（DMEM）的权限的多个属性（ATi）的装置; 存储规定数量属性的缓存存储器（CMEM，CMC）; 以及当高速缓冲存储器内部不存在属性时，在存储装置（DMEM，ATMEM）内检索属性的同步属性检索电路（ASC2）。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004140360A

公开(公告)日：2004-05-13

申请号：JP2003352097

申请日：2003-10-10

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： GRIS YVON

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/22 ,  H01L21/263 ,  H01L21/265 ,  H01L21/822 ,  H01L27/08

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: PROBLEM TO BE SOLVED: To provide a process of performing selective doping for a resistance element predetermined in an electronic chip.
SOLUTION: This process is constituted of three phases. At the first phase, several elements of a pattern are selectively electrified, at the second phase, doping atoms are applied to the electrified elements, and at the third phase, a dopant is permeated to perform an annealing process which is intended to activate it.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003248578A

公开(公告)日：2003-09-05

申请号：JP2002347277

申请日：2002-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  BARDOUILLET MICHEL ,  PLAZA LAURENT

IPC: G06K19/10 ,  G06F7/58 ,  G07F7/10 ,  G09C1/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for generating a secret quantity based on an identifier of an integrated circuit. SOLUTION: A first digital word is generated from a physical parameter network, and the first word is submitted to at least one shift register, the output of the shift register generating the secret quantity. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003243525A

公开(公告)日：2003-08-29

申请号：JP2002257486

申请日：2002-09-03

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE ,  WUIDART LUC ,  BARDOUILLET MICHEL ,  BALTHAZAR PIERRE

IPC: G01K7/00 ,  G06F12/14 ,  G06F13/42 ,  G06F21/06 ,  G06K19/073 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for detecting the variation of at least one environmental parameter of an integrated circuit. SOLUTION: A propagation delay of an edge in a delay element sensitive to the variation of the environmental parameter is measured to compare a present or a measured delay with at least one reference value. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003229755A

公开(公告)日：2003-08-15

申请号：JP2002261496

申请日：2002-09-06

Applicant: ST MICROELECTRONICS SA

Inventor： CARANANA JOEL

IPC: G06F3/00 ,  G06F13/40 ,  H03K5/151 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide a control circuit for controlling serial cables having approximately the same rise and decay times. SOLUTION: A bus interface comprises a first circuit, based on a first pair of transistors (10 and 20) of opposite types, having control electrode and a common electrode provided with a first output potential (D+). A second circuit comprises a second pair of transistors (30 and 40) of opposite types, having a common electrode for providing a second potential (D-) by switching in opposite direction from the former. This device comprises first capacitive coupling means for feeding a portion of the signal existing at the first potential (D+) back into the control electrode at the second transistor pair and second capacitive coupling means for feeding a portion of the signal existing at the second potential (D-) back into the control electrodes of the first transistor pair. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003228707A

公开(公告)日：2003-08-15

申请号：JP2002302854

申请日：2002-10-17

Applicant: ST MICROELECTRONICS SA

Inventor： TISSE CHRISTEL-LOIC ,  BARBEYRAC DAMIEN

IPC: G06T7/00 ,  G06K9/00 ,  G06K9/48 ,  G06K9/52 ,  H04N1/41 ,  H04N7/30

Abstract: PROBLEM TO BE SOLVED: To provide a method for coding in frequency, module and phase a digital representation, in the space field, of a ring-shaped element. SOLUTION: The method includes the steps of applying to any point of the element a polar conversion at constant angle, whereby the element is unfolded in rectangular shape; transferring, to the frequency field, any point of the converted rectangular shape by means of a Fourier transform; filtering the discrete data resulting from the transfer by means of at least one real, bidimensional, band-pass filter, oriented along the phase axis; applying a Hilbert transform to the filtering results; applying an inverse Fourier transform to the results of the Hilbert transform; and extracting phase and module information in the space field. COPYRIGHT: (C)2003,JPO