公开(公告)号：KR1020040066999A

公开(公告)日：2004-07-30

申请号：KR1020030003935

申请日：2003-01-21

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  이수근 ,  이경우

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a dual damascene interconnection pattern of a semiconductor device is provided to prevent or minimize a node separation defect by compensating for a peeled part of the upper part of an interlayer dielectric with a hard mask or a trench opening while using a capping layer. CONSTITUTION: The dual damascene interconnection pattern is formed by using the first and second hard masks. After the second opening for extending the first opening of a via is formed as a trench type. Before a via etch blocking layer gets open, a capping layer(30) for compensating for the peeled portion of the upper part of the interlayer dielectric(8) with the second opening is formed.

Abstract translation: 目的：提供一种用于形成半嵌装置的双镶嵌互连图案的方法，以通过用硬掩模或沟槽开口补偿层间电介质的上部的剥离部分来防止或最小化节点分离缺陷，同时使用 盖层 构成：通过使用第一和第二硬掩模形成双镶嵌互连图案。 在用于延伸通孔的第一开口的第二开口形成沟槽型之后。 在通孔蚀刻阻挡层开放之前，形成用于利用第二开口补偿层间电介质（8）的上部的剥离部分的覆盖层（30）。

公开(公告)号：KR1020040013165A

公开(公告)日：2004-02-14

申请号：KR1020020045610

申请日：2002-08-01

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  이수근 ,  이경우

IPC: H01L21/28

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877

Abstract: PURPOSE: A method for forming a metal interconnection of a semiconductor device by a modified dual damascene process is provided to avoid a defect of an interconnection by preventing a recess in a via contact of a single damascene structure. CONSTITUTION: The first interlayer dielectric and the first and second material layers are sequentially formed on a semiconductor substrate(100) with a conductive layer(105) such that the first and second material layers include a material that reacts with a medium used in a process for eliminating photoresist. A photoresist layer of a pattern exposing a part of the upper surface of the second material layer is formed on the second material layer. The second material layer, the first material layer and the first interlayer dielectric are etched to form a via hole(160) by using the photoresist layer as an etch barrier layer(110). A part of the first material layer exposed to the via hole is changed while the photoresist layer is eliminated. The changed first material layer(135) is removed to form an opening larger than the via hole in the first material layer. The remaining second material layer is removed. A metal material is deposited to fill the via hole and the opening. A planarization process is performed until the first interlayer dielectric is exposed, so that a via contact is formed.

Abstract translation: 目的：提供通过改进的双镶嵌工艺形成半导体器件的金属互连的方法，以通过防止单个镶嵌结构的通孔接触中的凹陷来避免互连的缺陷。 构成：第一层间电介质和第一和第二材料层依次形成在具有导电层（105）的半导体衬底（100）上，使得第一和第二材料层包括与在工艺中使用的介质反应的材料 用于消除光刻胶。 在第二材料层上形成露出第二材料层的上表面的一部分的图案的光致抗蚀剂层。 通过使用光致抗蚀剂层作为蚀刻阻挡层（110），蚀刻第二材料层，第一材料层和第一层间电介质以形成通孔（160）。 暴露于通孔的第一材料层的一部分在光致抗蚀剂层被消除的同时被改变。 去除改变的第一材料层（135）以形成比第一材料层中的通孔大的开口。 剩余的第二材料层被去除。 沉积金属材料以填充通孔和开口。 进行平坦化处理，直到暴露第一​​层间电介质，从而形成通孔接触。

公开(公告)号：KR1020030061100A

公开(公告)日：2003-07-18

申请号：KR1020020001470

申请日：2002-01-10

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  이수근 ,  박기관 ,  이경우

IPC: H01L21/3205

Abstract: PURPOSE: A method for forming an interlayer dielectric pattern is provided to be capable of finely forming an opening portion and securing the vertical profile of the opening portion by using a spacer as an etching mask and using an organic polymer layer as the interlayer dielectric. CONSTITUTION: After forming a conductive layer pattern(110) at the upper portion of a semiconductor substrate, an interlayer dielectric and a hard mask layer are sequentially deposited on the entire surface of the resultant structure. Then, a hard mask pattern having the first opening portion(171) is formed by selectively patterning the hard mask layer for exposing the upper surface of the interlayer dielectric. A spacer(190) is formed at both sidewalls of the first opening portion. The upper surface of the conductive layer pattern is exposed by selectively etching the resultant structure using the spacer as an etching mask. Preferably, the interlayer dielectric is made of at least one selected from a group consisting of an organic polymer layer, a fluorine doped oxide layer, a carbon doped oxide layer, and a silicon oxide layer.

Abstract translation: 目的：提供一种用于形成层间电介质图案的方法，其能够通过使用间隔件作为蚀刻掩模并使用有机聚合物层作为层间电介质来精细地形成开口部分并确保开口部分的垂直轮廓。 构成：在半导体衬底的上部形成导电层图案（110）之后，在所得结构的整个表面上依次沉积层间电介质和硬掩模层。 然后，通过选择性地图案化用于暴露层间电介质的上表面的硬掩模层来形成具有第一开口部分（171）的硬掩模图案。 间隔件（190）形成在第一开口部分的两个侧壁处。 通过使用间隔物作为蚀刻掩模选择性地蚀刻所得到的结构来暴露导电层图案的上表面。 优选地，层间电介质由选自有机聚合物层，掺氟氧化物层，碳掺杂氧化物层和氧化硅层中的至少一种制成。

公开(公告)号：KR1020030000447A

公开(公告)日：2003-01-06

申请号：KR1020010036225

申请日：2001-06-25

Applicant: 삼성전자주식회사

Inventor： 김재학

IPC: G06Q40/02 ,  G06Q20/34

Abstract: PURPOSE: A wireless terminal having the payment information and a method for issuing a virtual card for the wireless terminal are provided to realize both the small amount advance payment and the big amount deferred payment in one terminal, to avoid the charge of an additional communication fee, and to relieve the burden of a mobile communication company to pay the big amount payment money. CONSTITUTION: A memory(602) stores the virtual card information of the plural virtual cards. An RF(Radio Frequency) IC(604) stores the virtual card information corresponding to the virtual card used for the payment, transmits the virtual card information with response to the request of a payment system, and receives the payment history. A menu part(606) selects the virtual card used for the payment among the plural virtual cards stored in the memory(602). A recording part stores the virtual card information about the virtual card selected by the menu part(608) in the RF IC(604).

Abstract translation: 目的：提供具有付费信息的无线终端和用于发送无线终端的虚拟卡的方法，以实现一个终端中的小额预付款和大额延期支付，以避免额外的通信费用 ，并减轻移动通信公司支付大笔款项的负担。 构成：存储器（602）存储多个虚拟卡的虚拟卡信息。 RF（射频）IC（604）存储对应于用于支付的虚拟卡的虚拟卡信息，并响应于支付系统的请求发送虚拟卡信息，并且接收支付历史。 菜单部（606）在存储器（602）中存储的多个虚拟卡中选择用于支付的虚拟卡。 记录部件将关于由菜单部分（608）选择的虚拟卡的虚拟卡信息存储在RF IC（604）中。

公开(公告)号：KR1020020088399A

公开(公告)日：2002-11-27

申请号：KR1020020027442

申请日：2002-05-17

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  김재학 ,  이수근

IPC: H01L21/28

CPC classification number: H01L21/76808 ,  H01L21/76813 ,  H01L21/76835

Abstract: PURPOSE: A method for forming a metal interconnection layer of a semiconductor device is provided to prevent formation of a metal oxide layer on a conductive layer in a process of removing a photoresist pattern, and prevent an ashing damage and profile fail of a via hole. CONSTITUTION: A stopper layer is formed on a semiconductor substrate. An insulation layer is formed on the stopper layer. A hard mask is formed on the insulation layer. A first photoresist pattern having a first aperture is formed to expose an upper partial portion of the hard mask. A partial via hole having a first width is formed by etching partially the hard mask and the insulation layer with the use of the first photoresist pattern as a mask. The first photoresist pattern is removed. An organic material layer is coated to fill the partial via hole. A second photoresist pattern having a second aperture is formed on the substrate comprised of the organic layer. The organic layer and hard mask layer are etched by using the second photoresist pattern as a mask and the second photoresist pattern and organic layer are removed. An interconnection region having the second width and a via hole having the first width are formed by etching the insulation layer with the use of the hard mask layer as an etch mask.

Abstract translation: 目的：提供一种用于形成半导体器件的金属互连层的方法，以在去除光致抗蚀剂图案的过程中防止在导电层上形成金属氧化物层，并且防止通孔的灰化损坏和轮廓失效。 构成：在半导体衬底上形成阻挡层。 在阻挡层上形成绝缘层。 在绝缘层上形成硬掩模。 形成具有第一孔的第一光致抗蚀剂图案以暴露硬掩模的上部局部部分。 通过使用第一光致抗蚀剂图案作为掩模，部分地蚀刻硬掩模和绝缘层，形成具有第一宽度的部分通孔。 去除第一光致抗蚀剂图案。 涂覆有机材料层以填充部分通孔。 具有第二孔径的第二光致抗蚀剂图案形成在由有机层组成的基板上。 通过使用第二光致抗蚀剂图案作为掩模蚀刻有机层和硬掩模层，并且去除第二光致抗蚀剂图案和有机层。 通过使用硬掩模层作为蚀刻掩模蚀刻绝缘层，形成具有第二宽度的互连区域和具有第一宽度的通孔。

公开(公告)号：KR1020020085722A

公开(公告)日：2002-11-16

申请号：KR1020010025573

申请日：2001-05-10

Applicant: 삼성전자주식회사

Inventor： 이수근 ,  신홍재 ,  이경우 ,  김재학

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

Abstract: PURPOSE: A metallization method of a semiconductor device is provided to prevent damage of a lower conductive layer when forming a via hole and a trench using dual damascene by using a protection layer made of SOD(Spin On Dielectric). CONSTITUTION: A first etch stopper(410) is formed on a lower conductive layer(300) formed on a semiconductor substrate(100). A first interlayer dielectric(510) and a second etch stopper(450) are sequentially formed on the first etch stopper. A second interlayer dielectric(550) is formed on the second etch stopper. A via hole(710) is formed to expose the lower conductive layer(300) by sequentially etching the second interlayer dielectric(550), the second etch stopper(450) and the first interlayer dielectric(510) using the first etch stopper(410). A protection layer is formed at the bottom of the via hole(710) so as to protect the first etch stopper(410). A trench(750) connected to the via hole is formed by selectively etching the second interlayer dielectric(550) using the second etch stopper(450). After removing the protection layer, the exposed first etch stopper(410) is then removed. Then, an upper conductive layer(900) is formed to fill in the via hole and the trench. At the time, an SOD film, such as HSQ(Hydro SilisesQuioxane) is used as the protection layer.

Abstract translation: 目的：提供半导体器件的金属化方法，以通过使用由SOD（旋转介质）制成的保护层，在使用双镶嵌形成通孔和沟槽时防止下导电层的损坏。 构成：在形成在半导体衬底（100）上的下导电层（300）上形成第一蚀刻停止层（410）。 在第一蚀刻停止器上依次形成第一层间电介质（510）和第二蚀刻停止件（450）。 在第二蚀刻停止件上形成第二层间电介质（550）。 通过使用第一蚀刻停止器（410）依次蚀刻第二层间电介质（550），第二蚀刻停止器（450）和第一层间电介质（510），形成通孔（710）以暴露下导电层（300） ）。 在通孔（710）的底部形成保护层，以保护第一蚀刻停止件（410）。 通过使用第二蚀刻停止器（450）选择性蚀刻第二层间电介质（550）来形成连接到通孔的沟槽（750）。 在去除保护层之后，然后去除暴露的第一蚀刻停止件（410）。 然后，形成上导电层（900）以填充通孔和沟槽。 此时，使用SOD膜，例如HSQ（Hydro SilisesQuioxane）作为保护层。

公开(公告)号：KR1020020008604A

公开(公告)日：2002-01-31

申请号：KR1020000042416

申请日：2000-07-24

Applicant: 삼성전자주식회사

Inventor： 김홍근 ,  김재학

IPC: H01L21/31

Abstract: PURPOSE: A method for forming an insulating layer of a semiconductor device is provided to form an insulating layer by using an HSQ(Hydrogen SilsesQuioxane) layer. CONSTITUTION: An HSQ layer(102) is formed on a semiconductor substrate(100). The HSQ layer(102) is formed by using a spin coating method. The HSQ layer(102) is exposed and oxidized by a solution including amine or a gas. A protective layer including a silica component is formed on the HSQ layer(102) by oxidizing the HSQ layer(102). The HSQ layer(102) is protected by the protective layer including the silica component. The amine is removed from a surface of the HSQ layer by performing a cleaning process. A curing process is performed under a nitrogen gas atmosphere. A photo-resist layer is formed on the protective layer. A photo-resist pattern is formed by patterning the photo-resist layer. An opening(106) is formed by etching the protective layer and the HSQ layer. The photo-resist pattern is removed by performing an ashing process.

Abstract translation: 目的：提供一种用于形成半导体器件的绝缘层的方法，以通过使用HSQ（氢化硅氧烷）层形成绝缘层。 构成：在半导体衬底（100）上形成HSQ层（102）。 HSQ层（102）通过使用旋涂法形成。 HSQ层（102）被包括胺或气体的溶液暴露并氧化。 通过氧化HSQ层（102），在HSQ层（102）上形成包含二氧化硅成分的保护层。 HSQ层（102）由包括二氧化硅组分的保护层保护。 通过进行清洗处理，从HSQ层的表面除去胺。 在氮气气氛下进行固化处理。 在保护层上形成光刻胶层。 通过图案化光致抗蚀剂层形成光刻胶图案。 通过蚀刻保护层和HSQ层形成开口（106）。 通过灰化处理去除光刻胶图案。

公开(公告)号：KR1020010063022A

公开(公告)日：2001-07-09

申请号：KR1019990059855

申请日：1999-12-21

Applicant: 삼성전자주식회사

Inventor： 김재학

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing a contact hole of a semiconductor device using a low dielectric layer as an insulation layer is provided to eliminate the necessity of a dry etching process for etching the insulation layer having low permittivity, and to prevent a bowing phenomenon occurring in a sidewall portion of a contact hole without the dry etching process. CONSTITUTION: A photoresist layer pattern is formed on a lower layer(100) wherein a contact is to be formed. The first insulation layer(120) is formed on the lower layer and the photoresist layer pattern. The second insulation layer(130) having low permittivity is formed on the first insulation layer. A portion of the first and second insulation layers is eliminated to expose an upper surface of the photoresist layer pattern. The photoresist layer pattern is removed to form a contact hole(150) exposing a portion of the lower layer.

Abstract translation: 目的：提供一种使用低电介质层作为绝缘层的半导体器件的接触孔的制造方法，以消除用于蚀刻具有低介电常数的绝缘层的干蚀刻工艺的必要性，并且防止发生弯曲现象 没有干蚀刻工艺的接触孔的侧壁部分。 构成：在要形成接触的下层（100）上形成光致抗蚀剂图案。 第一绝缘层（120）形成在下层和光致抗蚀剂层图案上。 在第一绝缘层上形成具有低介电常数的第二绝缘层（130）。 去除第一和第二绝缘层的一部分以露出光致抗蚀剂层图案的上表面。 去除光致抗蚀剂层图案以形成暴露下层的一部分的接触孔（150）。

公开(公告)号：KR1020000051647A

公开(公告)日：2000-08-16

申请号：KR1019990002209

申请日：1999-01-25

Applicant: 삼성전자주식회사

Inventor： 김동빈 ,  장삼복 ,  김재학 ,  선용균

IPC: H01L21/78

Abstract: PURPOSE: An apparatus for cutting a mounting tape is provided which prevents the generation of remnants of the mounting tape cause during the process of cutting the mounting tape, thus blocks the broken phenomenon of a wafer in advance. CONSTITUTION: According to an apparatus(100) for cutting a mounting tape(6), a cutter supporting frame where a cutter(50) is installed is divided into a main frame(10) and a sub frame(20) possessing oblique surfaces(11,21) with an angle. In this case, the sub frame is installed on the main frame as facing its oblique surface so that it can be moved, and the main frame is fixed to an end part of a cutter rotation axis(30). Then, when the descending operation of the main frame is proceeded by the descending operation of the cutter rotation axis, the main frame pushes the sub frame to the inside of a wafer/wafer ring assembly. In this case, the cutter installed in the sub frame is pushed to the wafer/wafer ring assembly by the push operation of the main frame. In this case, the cutter is not pushed from the initial contact position of a mounting tape, although the cutter is contacted with the mounting tape and the cutter receives a certain contact impact. In addition, although the rotation operation is proceeded more than one time, the overall rotation slope is maintained uniformly. Finally, the remnants of the mounting tape generated by the change of the rotation slope of the cutter are prevented in advance.

Abstract translation: 目的：提供一种用于切割安装带的装置，其防止在切割安装带的过程中产生安装带的残留物，从而预先阻止晶片的断裂现象。 构成：根据用于切割安装带（6）的装置（100），安装有切割器（50）的切割器支撑框架被分割成具有倾斜表面的主框架（10）和子框架（20） 11,21）。 在这种情况下，子框架面向其倾斜表面安装在主框架上，使得其可以移动，并且主框架固定到切割器旋转轴线（30）的端部。 然后，当通过切割器旋转轴的下降操作进行主框架的下降操作时，主框架将子框架推动到晶片/晶片环组件的内部。 在这种情况下，通过主框架的推动操作将安装在副框架中的刀具推到晶片/晶片环组件。 在这种情况下，切割器不会从安装带的初始接触位置推动，尽管切割器与安装带接触，并且切割器受到一定的接触冲击。 此外，虽然旋转操作进行了一次以上，但总体旋转斜率保持均匀。 最后，预先防止由于切割器的旋转斜率的改变而产生的安装带的残留物。

公开(公告)号：KR1020090100191A

公开(公告)日：2009-09-23

申请号：KR1020080044545

申请日：2008-05-14

Applicant: 삼성전자주식회사 ,  글로벌파운드리즈 싱가포르 피티이 엘티디

Inventor： 김재학 ,  리,징후이 ,  리우,우핑 ,  위도도,조니

IPC: H01L21/28

CPC classification number: H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L2221/1063

Abstract: PURPOSE: A method of fabricating a semiconductor device including a conductive pattern having continuous surface boundaries is provided to form the conductive pattern having no discontinuous boundary. CONSTITUTION: The first conductive pattern(110) is formed on the substrate. The etch stop layer is formed on the first conductive patterns. The interlayer insulating film(120) is formed on the etch stop layer. The hard mask is formed on the interlayer insulating film. The via hole is formed by exposing selectively the etch stop layer. The width of the via hole is wider than that of the interlayer insulating film. The reactive layer is formed in the side wall of the interlayer insulating film exposed by the via hole. The reactive layer is removed. The second conductive patterns are formed by filling a conductor in the via hole.

Abstract translation: 目的：提供一种制造包括具有连续表面边界的导电图案的半导体器件的方法，以形成不具有不连续边界的导电图案。 构成：第一导电图案（110）形成在基板上。 蚀刻停止层形成在第一导电图案上。 层间绝缘膜（120）形成在蚀刻停止层上。 硬掩模形成在层间绝缘膜上。 通孔是通过选择性地暴露蚀刻停止层而形成的。 通孔的宽度比层间绝缘膜宽。 反应层形成在由通孔露出的层间绝缘膜的侧壁中。 去除反应层。 通过在导孔中填充导体来形成第二导电图案。