公开(公告)号：KR1020160135913A

公开(公告)日：2016-11-29

申请号：KR1020150069350

申请日：2015-05-19

Applicant: 삼성전자주식회사

Inventor： 이하영 ,  이준원 ,  김문준 ,  김홍근 ,  이종명 ,  최병덕

IPC: H01L21/316 ,  H01L21/24 ,  H01L21/3205

CPC classification number: H01L28/91 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76828 ,  H01L23/5223 ,  H01L23/53295

Abstract: 두께방향을따라연속적으로변화하는도판트농도구배를가지는도핑된몰드막을형성하고, 도핑된몰드막의일부를상기두께방향을따라식각하여홀을형성한다. 홀의내벽을따라연장되는전극을형성한다. 전극은절연패턴에형성된관통홀내에서절연패턴의측벽에접하는제1 외벽면과, 절연패턴의상면에접하고횡방향으로연장되는제2 외벽면과, 제2 외벽면을사이에두고제1 외벽면과이격되고절연패턴상에서기판과멀어지는방향으로연장되어있는제3 외벽면을가진다.

Abstract translation: 掺杂的模具膜在掺杂的模具膜中形成掺杂剂浓度梯度，其厚度方向连续变化，并且在厚度方向上蚀刻一部分掺杂的模具膜以形成孔，从而沿着 孔的内壁。 如此形成的电极包括第一外壁表面，第二外壁表面和第三外壁表面，其中第一外壁表面与形成在通孔中的通孔中的基板上形成的绝缘图案的侧壁接触 绝缘图案; 所述第二外壁表面与所述绝缘图案的顶表面接触并沿横向方向延伸; 所述第三外壁表面与所述第一外壁表面间隔开，而所述第二外壁表面之间具有第二外壁表面; 并且第三外壁表面在远离基底的方向上在绝缘图案上延伸。

公开(公告)号：KR1020130075119A

公开(公告)日：2013-07-05

申请号：KR1020110143340

申请日：2011-12-27

Applicant: 삼성전자주식회사

Inventor： 김홍근 ,  김동영 ,  김충웅

IPC: G01N35/00 ,  G01N21/75 ,  G01N33/483

CPC classification number: G01N35/1081 ,  G01N35/00069

Abstract: PURPOSE: An apparatus for sample analysis is provided to stop a disc in a correct position only with a protrusion formed on a lower surface of the disc and a stopper formed on a slider. CONSTITUTION: An apparatus for sample analysis (1) comprises: a disc (10) including at least one detection area and rotatably arranged with a rotary shaft as a center; an optical sensor configured to sense a reaction result appeared in at least one detection area; at least one position determination protrusions (131-133) which is formed to protrude in one side of the disc; a slider (30) which is movably arranged to at least one direction among the outer side and the inner side of a radius direction of the disc; a stopper (320) which is mounted on a slider, configured to stop a rotation of the disc by blocking at least one position determination protrusions.

Abstract translation: 目的：提供一种用于样品分析的装置，用于仅在形成在盘的下表面上的突起和形成在滑块上的止动件上将盘停止在正确位置。 构成：用于样品分析的装置（1）包括：盘（10），其包括至少一个检测区域，并以旋转轴为中心可旋转地布置; 光传感器，被配置为感测在至少一个检测区域中出现的反应结果; 形成为在所述盘的一侧突出的至少一个位置确定突起（131-133） 滑块（30），其可移动地布置在所述盘的半径方向的外侧和内侧中的至少一个方向上; 安装在滑块上的止动件（320），其被构造成通过阻挡至少一个位置确定突起来停止所述盘的旋转。

公开(公告)号：KR1020120091592A

公开(公告)日：2012-08-20

申请号：KR1020110011453

申请日：2011-02-09

Applicant: 삼성전자주식회사

Inventor： 김홍근 ,  이용구 ,  이영균

IPC: G01N35/00 ,  G01N33/48 ,  G01N33/483

Abstract: PURPOSE: A disk type microfluidic device is provided to save production costs by omitting a separate device for detecting the insertion error of the disk type microfluidic device. CONSTITUTION: A disk type microfluidic device(10) includes a disk type body(11) and a penetrating hole(118). The penetrating hole penetrates the center part of the body such that a driving unit(100) is combined with the body. The penetrating hole is vertically asymmetric such that the driving unit is combined with the specific one direction of the body. The driving unit includes a turntable(106) and a spindle motor(102). The turntable is combined with the penetrating hole. The spindle motor rotates the turntable. At least one stepped part is arranged at the penetrating hole in order to prevent the insertion of the turntable.

Abstract translation: 目的：提供盘式微流体装置，通过省略单独的装置来检测盘式微流体装置的插入误差来节省生产成本。 构成：盘式微流体装置（10）包括盘形体（11）和穿透孔（118）。 穿透孔穿透身体的中心部分，使得驱动单元（100）与身体组合。 穿透孔是垂直不对称的，使得驱动单元与身体的具体的一个方向组合。 驱动单元包括转盘（106）和主轴马达（102）。 转盘与穿透孔结合在一起。 主轴电机旋转转盘。 至少一个台阶部分布置在穿透孔处，以防止转盘的插入。

公开(公告)号：KR1020120013614A

公开(公告)日：2012-02-15

申请号：KR1020100075693

申请日：2010-08-05

Applicant: 삼성전자주식회사

Inventor： 최용순 ,  이준원 ,  최길현 ,  홍은기 ,  김홍근 ,  이하영

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

CPC classification number: H01L21/76229 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11531 ,  H01L27/11548

Abstract: PURPOSE: A manufacturing method of a semiconductor device which includes various device separation regions is provided to improve productivity and yield by not affecting conductive structures from the various device separation regions. CONSTITUTION: A first trench(120) and a second trench(125) are formed within a semiconductor substrate(101). The first trench is formed within the semiconductor substrate with a first width(W1) and a first depth(D1). The second trench is formed within the semiconductor substrate with a first width(W2) and a first depth(D2). A first insulating material(130) is formed in order to completely fill the inside of the first trench. A second insulating material(140) is formed on the first insulating materials in the inside of the second trench.

Abstract translation: 目的：提供包括各种器件分离区域的半导体器件的制造方法，以通过不影响各种器件分离区域的导电结构来提高生产率和产率。 构成：在半导体衬底（101）内形成第一沟槽（120）和第二沟槽（125）。 第一沟槽形成在半导体衬底内，具有第一宽度（W1）和第一深度（D1）。 第二沟槽形成在半导体衬底内，具有第一宽度（W2）和第一深度（D2）。 形成第一绝缘材料（130）以完全填充第一沟槽的内部。 第二绝缘材料（140）形成在第二沟槽内部的第一绝缘材料上。

公开(公告)号：KR100823703B1

公开(公告)日：2008-04-21

申请号：KR1020060108098

申请日：2006-11-03

Applicant: 삼성전자주식회사

Inventor： 최용순 ,  김홍근 ,  최종완 ,  백은경 ,  구주선

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L27/11521 ,  H01L29/7881

Abstract: An isolation structure, a forming method thereof, a semiconductor device having the same and a method for fabricating the semiconductor device are provided to easily bury trenches, while preventing deterioration of a tunnel oxide layer pattern and oxidization of a floating gate. Trenches are formed on a substrate(100), and an inner wall oxide layer(125) is formed on a sidewall and a bottom surface of the trench. A liner layer pattern(140b) having a first oxide layer pattern(130b) and a second oxide layer pattern(135b) is formed on the inner wall oxide layer. A barrier layer pattern(150b) is formed on the liner layer pattern, and an isolation layer pattern(160b) is formed on the barrier layer pattern to fill a portion of the trench. A compensation layer is formed on the liner layer pattern, the barrier layer pattern and the isolation layer pattern to fully fill the trench.

Abstract translation: 提供隔离结构，其形成方法，具有该半导体器件的半导体器件和制造半导体器件的方法能够容易地埋入沟槽，同时防止隧道氧化物层图案的劣化和浮栅的氧化。 沟槽形成在基板（100）上，并且内壁氧化物层（125）形成在沟槽的侧壁和底表面上。 在内壁氧化物层上形成具有第一氧化物层图案（130b）和第二氧化物层图案（135b）的衬垫层图案（140b）。 在衬垫层图案上形成阻挡层图案（150b），并且在阻挡层图案上形成隔离层图案（160b）以填充沟槽的一部分。 在衬垫层图案，阻挡层图案和隔离层图案上形成补偿层以完全填充沟槽。

公开(公告)号：KR1020060131125A

公开(公告)日：2006-12-20

申请号：KR1020050051334

申请日：2005-06-15

Applicant: 삼성전자주식회사

Inventor： 이기성 ,  이재형 ,  김홍근

IPC: H01L21/20

CPC classification number: C23C16/45525 ,  C23C16/45565 ,  C23C16/45574

Abstract: A gas supply nozzle for an atomic layer deposition process and a gas supply method using the same are provided to prevent a back flow effect of second reaction gas by supplying the first and second reaction gases through different gas nozzles. A first nozzle(306a) is used for a first flow process of a first reaction gas. The first nozzle has a two-stage structure. An upper part of the first nozzle is narrower than a lower part of the first nozzle. A second nozzle(306b) is used for a second flow process of a second reaction gas. The amount of the second reaction gas is larger than the amount of the first reaction gas. The second nozzle is used for surrounding the upper part of the first nozzle narrower than the lower part of the first nozzle.

Abstract translation: 提供了用于原子层沉积工艺的气体供应喷嘴和使用其的气体供应方法，以通过将第一和第二反应气体通过不同的气体喷嘴供应来防止第二反应气体的回流效应。 第一喷嘴（306a）用于第一反应气体的第一流动过程。 第一喷嘴具有两级结构。 第一喷嘴的上部比第一喷嘴的下部窄。 第二喷嘴（306b）用于第二反应气体的第二流动过程。 第二反应气体的量比第一反应气体的量大。 第二喷嘴用于围绕比第一喷嘴的下部窄的第一喷嘴的上部。

公开(公告)号：KR1020040074348A

公开(公告)日：2004-08-25

申请号：KR1020030009917

申请日：2003-02-17

Applicant: 삼성전자주식회사

Inventor： 김홍근 ,  홍은기 ,  구주선

IPC: H01L21/762

CPC classification number: H01L51/0537 ,  H01L21/31051 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/76224

Abstract: PURPOSE: A method for forming a thin film and a method for forming a trench isolation layer using the same are provided to reduce a defect of a SOG layer having an improved burying characteristic by performing only a soft baking process. CONSTITUTION: An SOG layer(34a) is formed by coating an SOG solution having polysilazane on the surface of a substrate(30) having a stepped part(32). The SOG layer is used for burying a recess formed by the stepped part. A soft baking process for the SOG layer is performed. An etch-back process for the SOG layer is performed. An insulating layer(36) is laminated on the substrate after the etch-back process for the SOG layer is performed.

Abstract translation: 目的：提供一种形成薄膜的方法和使用该方法形成沟槽隔离层的方法，通过仅进行软烘烤处理来减少具有改善的掩埋特性的SOG层的缺陷。 构成：通过在具有阶梯部（32）的基板（30）的表面上涂布具有聚硅氮烷的SOG溶液形成SOG层（34a）。 SOG层用于埋设由阶梯部形成的凹部。 进行SOG层的软烘烤处理。 执行用于SOG层的回蚀处理。 在执行SOG层的回蚀处理之后，在基板上层压绝缘层（36）。

公开(公告)号：KR1020040050971A

公开(公告)日：2004-06-18

申请号：KR1020020078779

申请日：2002-12-11

Applicant: 삼성전자주식회사

Inventor： 김홍근 ,  나규태 ,  홍은기 ,  구주선

IPC: H01L21/31

CPC classification number: H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76224 ,  H01L21/76229

Abstract: PURPOSE: A gap fill method for manufacturing a semiconductor device is provided to be capable of filling an insulating layer in a gap region without voids or grooves. CONSTITUTION: A pattern having a gap region is formed on a semiconductor substrate(50). A lower oxide layer(62) is formed on the entire surface of the resultant structure for filling the gap region. An etch-back process is carried out on the lower oxide layer. At this time, the lower oxide layer exists at the lower portion of the gap region. An upper oxide layer(64) is selectively deposited on the lower oxide layer. Preferably, the pattern is completed by forming a hard mask pattern on the semiconductor substrate for partially exposing the semiconductor substrate and forming a trench region(54) in the semiconductor substrate using the hard mask pattern as an etching mask. Preferably, the upper oxide layer is formed by using O3 and TEOS(Tetra Ethyl Ortho Silicate) as source gas at the pressure of 200-760 torr and at the temperature of 300-560 °C.

Abstract translation: 目的：提供一种用于制造半导体器件的间隙填充方法，以能够在没有空隙或凹槽的间隙区域中填充绝缘层。 构成：在半导体衬底（50）上形成具有间隙区域的图案。 在所得结构的整个表面上形成下部氧化物层（62），用于填充间隙区域。 在低氧化物层上进行回蚀处理。 此时，低氧化物层存在于间隙区域的下部。 选择性地在低氧化物层上沉积上氧化物层（64）。 优选地，通过在半导体衬底上形成硬掩模图案以部分地暴露半导体衬底并且使用硬掩模图案作为蚀刻掩模在半导体衬底中形成沟槽区域（54）来完成图案。 优选地，通过使用O3和TEOS（四乙基原硅酸盐）作为源气体，在200-760乇的压力和在300-560℃的温度下形成上部氧化物层。

公开(公告)号：KR100434187B1

公开(公告)日：2004-06-04

申请号：KR1020010049779

申请日：2001-08-18

Applicant: 삼성전자주식회사

Inventor： 홍은기 ,  이주범 ,  구주선 ,  김명철 ,  김홍근

IPC: H01L21/316

CPC classification number: H01L21/76897 ,  H01L21/31051 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76834 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/935 ,  H01L2924/00

Abstract: Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device. Thus, a planar silicon oxide layer is formed between conductive patterns having a fine interval therebetween without creating a void. In addition, a metal layer pattern, which acts as a conductor in the conductive patterns, can be prevented from being oxidized when the silicon oxide layer is formed.

Abstract translation: 公开了一种用于形成半导体器件的氧化硅层的方法，所述半导体器件能够在精细导电图案之间绝缘而不会导致工艺失败，并且用于形成具有氧化硅层的布线。 在半导体衬底上形成导电图案之后，在导电图案上和半导体衬底上依次形成抗氧化层。 抗氧化层防止氧化剂渗透到导电图案和半导体衬底中。 通过在埋入导电图案的同时在抗氧化层上涂覆可回流氧化材料来形成可回流氧化物层。 氧化硅层通过对可回流氧化物层进行热处理而形成。 然后，对导体图案和暴露于半导体基板的抗氧化层之间填充的氧化硅层进行蚀刻，以形成接触孔，由此形成半导体器件的布线。 因此，在具有精细间隔的导电图案之间形成平面氧化硅层而不会产生空隙。 此外，当形成氧化硅层时，可以防止用作导电图案中的导体的金属层图案被氧化。

公开(公告)号：KR1020030015931A

公开(公告)日：2003-02-26

申请号：KR1020010049779

申请日：2001-08-18

Applicant: 삼성전자주식회사

Inventor： 홍은기 ,  이주범 ,  구주선 ,  김명철 ,  김홍근

IPC: H01L21/316

CPC classification number: H01L21/76897 ,  H01L21/31051 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76834 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/935 ,  H01L2924/00

Abstract: PURPOSE: A method for forming a silicon oxide layer of a semiconductor device and a method for forming a wire having a silicon oxide layer are provided to insulate patterns without forming a void between the patterns arrayed according to a fine interval. CONSTITUTION: A plurality of conductive patterns(32) are formed on a semiconductor substrate(30). The conductive patterns(32) are formed with a metal layer pattern(32a) and a nitride layer pattern(32b). The metal layer pattern(32a) is used as a conductor. A protective oxide layer is formed on the conductive patterns(32) and the semiconductor substrate(30). A floating oxide layer is formed by coating a floating oxide on the conductive patterns(32) having the protective oxide layer. A silicon oxide layer(40) is formed by performing a thermal process for the floating oxide layer.

Abstract translation: 目的：提供一种用于形成半导体器件的氧化硅层的方法和用于形成具有氧化硅层的布线的方法，以在不形成根据细微间隔排列的图案之间的空隙的情况下绝缘图案。 构成：在半导体衬底（30）上形成多个导电图案（32）。 导电图案（32）由金属层图案（32a）和氮化物层图案（32b）形成。 金属层图案（32a）用作导体。 在导电图案（32）和半导体衬底（30）上形成保护氧化层。 通过在具有保护氧化物层的导电图案（32）上涂覆浮动氧化物来形成浮动氧化物层。 通过对浮动氧化物层进行热处理形成氧化硅层（40）。