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公开(公告)号：KR1020080074611A
公开(公告)日：2008-08-13
申请号：KR1020070013953
申请日：2007-02-09
Applicant: 삼성전자주식회사
IPC: H01L23/62
CPC classification number: H01L23/5256 , H01L21/268 , H01L21/76897 , H01L21/78
Abstract: A semiconductor apparatus is provided to minimize a defect rate of a semiconductor memory apparatus by cutting a fuse with a laser or an electrical manner. A fuse unit includes a semiconductor substrate(10), a first fuse(F1), a first fuse formed on the first fuse, and a contact(C1) coupling the first fuse and a second fuse. An interlayer dielectric(20) is formed on the semiconductor substrate. The first fuse is formed on the interlayer dielectric. An inter-metal dielectric(30) having a contact hole is formed on the first fuse. The contact hole exposes a part of an upper surface of the first fuse. The contact coupling the first fuse to the second fuse is formed on the contact hole. The first fuse and the second fuse are serially connected by the contact. The second fuse is formed on the contact and the second interlayer dielectric. The second fuse is overlapped with the first fuse. A constant region of the second fuse is cut by a laser.
Abstract translation: 提供一种半导体装置，通过用激光或电气方式切割熔丝来最小化半导体存储装置的缺陷率。 熔丝单元包括半导体衬底（10），第一熔丝（F1），形成在第一熔丝上的第一熔丝以及将第一熔丝和第二熔丝耦合的触头（C1）。 在半导体衬底上形成层间电介质（20）。 第一个保险丝形成在层间电介质上。 在第一保险丝上形成具有接触孔的金属间电介质（30）。 接触孔暴露第一保险丝的上表面的一部分。 将第一保险丝耦合到第二保险丝的接触件形成在接触孔上。 第一个保险丝和第二个保险丝通过触点串联连接。 第二熔丝形成在触点和第二层间电介质上。 第二个保险丝与第一个保险丝重合。 第二个保险丝的恒定区域被激光切割。
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公开(公告)号：KR1020080025993A
公开(公告)日：2008-03-24
申请号：KR1020060090872
申请日：2006-09-19
Applicant: 삼성전자주식회사
IPC: H01L27/02
CPC classification number: H01L27/0285 , H01L27/0623 , H01L27/098
Abstract: A semiconductor device including an active resistor and a method for biasing the same are provided to maintain constantly the resistance of the active resistor by preventing a forward bias effect generated between a substrate and the active resistor. A semiconductor device includes a deep N-well region(30), N-well regions(42,44), a P-well region(50), and a first resistor(60). The deep N-well region is formed on a substrate. The N-well regions, which are formed on the deep N-well region, are connected to a first source voltage. The P-well region is formed on the deep N-well region. The first resistor is formed on the P-well region. The P-well region is connected to a second source voltage and the substrate through a second resistor(70).
Abstract translation: 提供一种包括有源电阻器及其偏置方法的半导体器件，以通过防止在衬底和有源电阻器之间产生的正向偏置效应来恒定地保持有源电阻器的电阻。 半导体器件包括深N阱区（30），N阱区（42,44），P阱区（50）和第一电阻（60）。 在衬底上形成深N阱区。 形成在深N阱区上的N阱区域连接到第一源极电压。 P阱区形成在深N阱区上。 第一电阻器形成在P阱区域上。 P阱区域通过第二电阻器（70）连接到第二源极电压和衬底。
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公开(公告)号：KR1020080025541A
公开(公告)日：2008-03-21
申请号：KR1020060090150
申请日：2006-09-18
Applicant: 삼성전자주식회사
IPC: G11C29/00
Abstract: A test control circuit for blocking direct current path in a wafer level test and a method thereof are provided to perform the wafer level test efficiently without loss of a voltage applied to a test pad. A test pad(110) applies a test voltage from the outside when a wafer level test for a memory device is performed. An input buffer(120) receives and outputs the test voltage to an internal circuit when the wafer level test is performed. A current blocking part(130) blocks a direct current path from the test pad to a ground voltage in response to a control signal when the wafer level test is performed.
Abstract translation: 提供一种用于在晶片级测试中阻止直流路径的测试控制电路及其方法，以有效地执行晶片级测试，而不会损失施加到测试焊盘的电压。 当执行存储器件的晶片级测试时，测试焊盘（110）从外部施加测试电压。 当执行晶片级测试时，输入缓冲器（120）接收并输出到内部电路的测试电压。 当执行晶片级测试时，电流阻挡部分（130）响应于控制信号阻止从测试焊盘到接地电压的直流路径。
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公开(公告)号：KR100773740B1
公开(公告)日：2007-11-09
申请号：KR1020060133162
申请日：2006-12-22
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/05 , H01L2224/04042 , H01L2224/05 , H01L2224/05554 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01079
Abstract: A pad having the same voltage level as that of a semiconductor substrate, and a semiconductor device including the same are provided to use the pad as a plug to prevent latch up of the semiconductor device, without installing a separate plug. A junction region(320) doped with high-concentration impurity ion is defined in a semiconductor substrate(310). A poly layer portion(350) is electrically connected to at least one portion of the junction region. A metal layer portion(330) is electrically connected to the poly layer portion, and receives the voltage applied from an exterior to transmit the voltage to the semiconductor substrate. The metal layer portion has at least one of metal layers(331,332,333).
Abstract translation: 提供具有与半导体衬底相同的电压电平的焊盘和包括该焊盘的半导体器件，以便在不安装单独的插头的情况下使用焊盘作为插头来防止半导体器件的闩锁。 在半导体衬底（310）中限定掺杂有高浓度杂质离子的结区（320）。 多层部分（350）电连接到连接区域的至少一部分。 金属层部分（330）电连接到多层部分，并且接收从外部施加的电压以将电压传输到半导体衬底。 金属层部分具有至少一个金属层（331,332,333）。
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公开(公告)号：KR100689850B1
公开(公告)日：2007-03-08
申请号：KR1020060013850
申请日：2006-02-13
Applicant: 삼성전자주식회사
IPC: H01L21/66
Abstract: An inspection apparatus for printed circuit board is provided to check whether solder cream is coated on a substrate uniformly by irradiating slit light onto the surface of the substrate and analyzing the light reflected on the surface of the substrate. A light scanning unit(200) scans slit light onto a surface of a substrate(10). A light receiving unit(300) receives light(R) reflected on the surface of the substrate. A camera(400) is used for sensing the reflected light of the light receiving unit. A transfer unit(100) transfers the substrate. An analysis unit(500) inspects a flatness state of the substrate by analyzing continuously the reflected light of the camera.
Abstract translation: 提供一种用于印刷电路板的检查设备，用于通过将狭缝光照射到基板表面上并分析在基板表面上反射的光来检查焊膏是否均匀地涂覆在基板上。 光扫描单元（200）将狭缝光扫描到衬底（10）的表面上。 光接收单元（300）接收在衬底表面上反射的光（R）。 照相机（400）用于感测光接收单元的反射光。 转印单元（100）转印基材。 分析单元（500）通过连续分析照相机的反射光来检查基板的平坦状态。
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Patent Agency Ranking
公开(公告)号：KR100687015B1
公开(公告)日：2007-02-27
申请号：KR1020010057804
申请日：2001-09-19
Applicant: 삼성전자주식회사
Inventor： 김정열
IPC: H01L21/027
CPC classification number: H01L21/67259 , G03F7/2028 , H01L21/67069 , H01L21/67115 , H01L21/681
Abstract: 본 발명은 반도체 웨이퍼상에 도포된 레지스트의 주변부를 정밀도 좋게 노광하기 위한 웨이퍼 주변부 노광 장치에 관한 것이며, 노광면의 높이의 변동에 관계없이 레지스트막의 주변부를 항상 적절하게 노출하는 것을 목적으로 한다. 반도체 웨이퍼(34)의 주변부를 향하여 노광광을 조사하는 광학부(36)를 구비한다. 광학부(36)는 광학부(36)의 하단부와, 반도체 웨이퍼(34)의 주변부와의 거리를 검출하는 집점 센서(37)를 구비한다. 상기 거리가 광학부(36)의 집점 거리에 일치하도록, 집점 센서(37)의 검출값에 의거하여 광학부(36)를 상하로 이동시키는 위치 조정 기구(38)를 구비한다.
반도체 웨이퍼, 광학부, 집점 센서, 위치 조정 기구, 위치 조정 모터-
公开(公告)号：KR1020070003243A
公开(公告)日：2007-01-05
申请号：KR1020050059046
申请日：2005-07-01
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/05 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/48 , H01L2224/48463 , H01L2924/00014 , H01L2224/05556 , H01L2924/00012
Abstract: A pad structure in a semiconductor device is provided to reduce capacitance by using at least two coil type metal layers spaced apart from each other. A pad structure is formed like a vertical structure. The pad structure is composed of at least two or more metal layers. The metal layers are formed like a coil type structure. The metal layers are spaced apart from each other. The metal layers are connected with each other by using contact portions(CT1,CT2). The contact portion is used for connecting a first inner end portion of a first metal layer with a second inner end portion of a second metal layer.
Abstract translation: 提供半导体器件中的焊盘结构，以通过使用彼此间隔开的至少两个线圈型金属层来减小电容。 衬垫结构形成为垂直结构。 垫结构由至少两个以上的金属层构成。 金属层形成为线圈型结构。 金属层彼此间隔开。 金属层通过使用接触部分（CT1，CT2）彼此连接。 接触部分用于将第一金属层的第一内端部分与第二金属层的第二内端部分连接。
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68.发明授权
公开(公告)号：KR100660888B1
公开(公告)日：2006-12-26
申请号：KR1020050107013
申请日：2005-11-09
Applicant: 삼성전자주식회사
Abstract: A semiconductor memory device comprising an extended operation mode and an apparatus for selecting the operation mode of the semiconductor memory device are provided to easily judge input/output characteristics of the semiconductor memory device, by using low speed test equipment. In a semiconductor memory device comprising a normal operation mode and an extended operation mode, input or output operation of input/output data is performed by using a normal data signal corresponding to input/output data of the semiconductor memory device operating synchronously with a reference internal clock and a normal data strobe signal synchronized with a pulse edge corresponding to the pulse edge of the normal data signal during the normal operation mode. During the extended operation mode, input or output operation of the input/output data is performed by using an extended data signal with extended time width from the normal data signal and an extended data strobe signal synchronized with a pulse edge corresponding to the pulse edge of the extended data signal. The rising edge or falling edge of the extended data strobe signal is synchronized with the rising edge or falling edge corresponding to the pulse edge of the extended data signal.
Abstract translation: 提供包括扩展操作模式的半导体存储器件和用于选择半导体存储器件的操作模式的设备，以通过使用低速测试设备容易地判断半导体存储器件的输入/输出特性。 在包括正常操作模式和扩展操作模式的半导体存储器件中，输入/输出数据的输入或输出操作通过使用与参考内部操作同步操作的半导体存储器件的输入/输出数据对应的正常数据信号来执行 时钟和在正常操作模式期间与对应于正常数据信号的脉冲边缘的脉冲边缘同步的正常数据选通信号。 在扩展操作模式期间，输入/输出数据的输入或输出操作通过使用具有来自正常数据信号的扩展时间宽度的扩展数据信号和与对应于正常数据信号的脉冲边沿的扩展数据选通信号同步 扩展的数据信号。 扩展数据选通信号的上升沿或下降沿与扩展数据信号的脉冲沿对应的上升沿或下降沿同步。
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公开(公告)号：KR1020060118892A
公开(公告)日：2006-11-24
申请号：KR1020050041322
申请日：2005-05-17
Applicant: 삼성전자주식회사
IPC: H03K5/14
CPC classification number: H03K5/133 , H03K2005/00058
Abstract: A delay circuit and a semiconductor device comprising the same are provided to delay an input signal through selected variable delay units only, by maintaining a minimum delay time constantly even though the number of the variable delay units increases. A plurality of variable delay units(21-2n) is connected serially. A driving unit(30) generates an output signal by assembling signals transmitted from the plurality of variable delay units. Each variable delay unit delays an output signal of a previous stage and then transmits the delayed output signal to a variable delay unit in a next stage when delay operation is enabled according to a control signal, and transmits the output signal of the previous stage to the driving part if the delay operation is disabled.
Abstract translation: 提供延迟电路和包括该延迟电路的半导体器件，以通过仅通过选择的可变延迟单元来延迟输入信号，即使可变延迟单元的数量增加，仍然保持最小延迟时间。 多个可变延迟单元（21-2n）被串联连接。 驱动单元（30）通过组合从多个可变延迟单元发送的信号来产生输出信号。 每个可变延迟单元延迟先前级的输出信号，然后根据控制信号使延迟操作在下一级发送延迟的输出信号到可变延迟单元，并将前一级的输出信号发送到 如果延迟操作被禁用，驱动部分。
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公开(公告)号：KR1020060106178A
公开(公告)日：2006-10-12
申请号：KR1020050028644
申请日：2005-04-06
Applicant: 삼성전자주식회사
IPC: H01L27/04
Abstract: 신호선 구조 및 그것을 구비한 반도체 집적회로가 개시되어 있다. 반도체 집적회로는 제 1 신호선 및 제 2 신호선을 구비한다. 제 1 신호선은 제 1 인버터 및 제 2 인버터에 결합되어 있다. 제 2 신호선은 제 1 신호선에 거의 평행하고 인접하며 제 3 인버터에 결합되어 있다. 제 1 신호선 상의 제 1 인버터와 제 1 신호선 상의 제 2 인버터 사이의 거리가 LE일 때, 제 2 신호선 상의 제 3 인버터는 제 1 인버터가 마주보는 제 2 신호선 상의 제 1 위치 점에서 0.3 LE 내지 0.7 LE 되는 지점에 위치한다.
따라서, 반도체 집적회로는 인접한 두 신호선에 인가되는 입력신호가 서로 동일한 위상을 가질 때나 반대의 위상을 가질 때나 출력신호의 스큐를 효과적으로 감소시킬 수 있다.
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