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公开(公告)号：KR1020010092914A
公开(公告)日：2001-10-27
申请号：KR1020000015581
申请日：2000-03-27
Applicant: 삼성전자주식회사
IPC: H01L21/68
Abstract: PURPOSE: An electrical static chuck is provided to minimize a deposition of particles between a wafer and a guide ring by forming a shadow ring between the wafer and the guide ring. CONSTITUTION: The electrostatic chuck(38) comprises a chuck(40) having a wafer loading surface and a guide ring(42) for surrounding the wafer loading surface. The electrostatic chuck(38) further includes a shadow ring(44) for coating interfaces between a wafer(W) and the guide ring(42). The shadow ring(44) further comprises a horizontal part(44a) parallel to the upper surface of the guide ring(42) and a vertical part(44b) contact with edge portions of the wafer(W). The shadow ring(44) is made of a silicon(Si), a SiC or a ceramic materials.
Abstract translation: 目的：提供电静电卡盘，以通过在晶片和导向环之间形成阴影环来最小化晶片和引导环之间的颗粒沉积。 构成：静电卡盘（38）包括具有晶片加载表面的卡盘（40）和用于围绕晶片加载表面的引导环（42）。 静电吸盘（38）还包括用于涂覆晶片（W）和导向环（42）之间的界面的阴影环（44）。 阴影环（44）还包括平行于引导环（42）的上表面的水平部分（44a）和与晶片（W）的边缘部分接触的垂直部分（44b）。 阴影环（44）由硅（Si），SiC或陶瓷材料制成。
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公开(公告)号：KR1020010038592A
公开(公告)日：2001-05-15
申请号：KR1019990046631
申请日：1999-10-26
Applicant: 삼성전자주식회사
IPC: H01L21/311
CPC classification number: H01L21/31116
Abstract: PURPOSE: A method of etching insulating layer is to employ new etching gas instead of an existing CxFy series gas when dry-etching silicon oxide to simplify an entire etching process, thereby improving etching process stability. CONSTITUTION: An insulating layer is formed on a semiconductor substrate. The insulating layer is wet-etched using a reaction gas of C4HxF8-xO. The x is an integral number of 0 to 4. The reaction gas includes a mixture gas of the C4HxF8-xO and the C4F8O(here, the x is an integral number of 1 to 4). Alternatively, the reaction gas is CxFy gas (the x is an integral number of 1 to 6 and the y is an integral number of 2 to 12), or CxHyFz gas (the x is an integral number of 1 to 6 and the y is an integral number of 1 to 4 and the z is an integral number of 2 to 10). The reaction gas further comprises an inert gas selected from a group of Ar, He, Kr and Xe. The insulating layer is formed of silicon oxide or silicon nitride.
Abstract translation: 目的：一种蚀刻绝缘层的方法是在干蚀刻氧化硅时采用新的蚀刻气体代替现有的CxFy系列气体，以简化整个蚀刻工艺，从而提高蚀刻工艺的稳定性。 构成：在半导体衬底上形成绝缘层。 使用C4HxF8-xO的反应气体对绝缘层进行湿式蚀刻。 x是0至4的整数。反应气体包括C4HxF8-xO和C4F8O的混合气体（这里x是1至4的整数）。 或者，反应气体为CxFy气体（x为1〜6的整数，y为2〜12的整数）或CxHyFz气体（x为1〜6的整数，y为 整数为1〜4，z为2〜10的整数）。 反应气体还包含选自Ar，He，Kr和Xe的惰性气体。 绝缘层由氧化硅或氮化硅形成。
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公开(公告)号：KR1020010036460A
公开(公告)日：2001-05-07
申请号：KR1019990043485
申请日：1999-10-08
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A method for manufacturing a cylindrical capacitor of a semiconductor device is provided to make the cylindrical capacitor on a substrate have uniform capacitance, by making cylindrical lower electrodes have uniform heights, and by making an upper surface of the cylindrical lower electrode have a round profile. CONSTITUTION: A lower electrode structure layer(80A) is formed which has an opening defining a cylindrical lower electrode(100A) on a substrate(10) having a transistor(20). A lower electrode layer is formed along a front surface of the lower electrode structure layer by a self-align method, wherein the lower electrode layer formed in the opening becomes a cylindrical type. An upper insulating layer(10) is formed on the lower electrode layer. An etch-back process is performed on a condition that etch selectivity of the lower electrode layer to the upper insulating layer and the lower electrode structure layer is more than 1:1, so that the cylindrical lower electrode of which an upper surface has a round profile is formed. The upper insulating and the lower electrode layer remaining on inner and outer sidewalls of the cylindrical lower electrode are eliminated to complete the cylindrical lower electrode. A dielectric layer and an upper electrode are formed on the entire structure having the cylindrical lower electrode.
Abstract translation: 目的：提供一种制造半导体器件的圆柱形电容器的方法，通过使圆柱形下电极具有均匀的高度，通过使圆柱形下电极的上表面具有圆形，从而使基板上的圆柱形电容器具有均匀的电容 个人资料。 构成：形成下电极结构层（80A），其具有在具有晶体管（20）的衬底（10）上限定圆柱形下电极（100A）的开口。 通过自对准方法沿着下电极结构层的前表面形成下电极层，其中形成在开口中的下电极层变为圆柱型。 在下电极层上形成上绝缘层（10）。 在下电极层对上绝缘层和下电极结构层的蚀刻选择性大于1:1的条件下进行回蚀工艺，使得其上表面具有圆形的圆柱形下电极 形状。 残留在圆筒形下电极的内壁和外侧壁上的上绝缘层和下电极层被去除以完成圆柱形下电极。 在具有圆柱形下电极的整个结构上形成电介质层和上电极。
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公开(公告)号：KR1020010017202A
公开(公告)日：2001-03-05
申请号：KR1019990032588
申请日：1999-08-09
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: PURPOSE: A trench isolating method for controlling a dent is provided to prevent the dent from being formed, by forming a spacer on a sidewall of an etching mask and a liner layer exposed to a corner of an isolating layer which becomes lower than the etching mask. CONSTITUTION: A predetermined depth of a semiconductor substrate(10) is etched to form a trench by using an etching mask. A liner layer is formed on the entire substrate including the trench. An insulating layer is filled in the trench having the liner layer. The semiconductor substrate is planarized and the insulating material formed in a portion except the trench is eliminated, so that an isolating layer(25) is formed only in the trench. A spacer(110) is formed on a sidewall of the liner layer exposed to a corner portion of the isolating layer of which a height becomes higher than the etching mask. A liner layer of a portion which is protruded higher than the etching mask and the substrate is eliminated.
Abstract translation: 目的：提供一种用于控制凹陷的沟槽隔离方法，以通过在蚀刻掩模的侧壁上形成间隔物和暴露于低于蚀刻掩模的隔离层的角部的衬垫层来防止形成凹坑 。 构成：通过使用蚀刻掩模蚀刻半导体衬底（10）的预定深度以形成沟槽。 衬垫层形成在包括沟槽的整个衬底上。 在具有衬里层的沟槽中填充绝缘层。 半导体衬底被平坦化，并且除了沟槽之外的部分中形成的绝缘材料被消除，使得仅在沟槽中形成隔离层（25）。 间隔物（110）形成在衬垫层的暴露于高度变得高于蚀刻掩模的隔离层的角部的衬里层的侧壁上。 省略了比蚀刻掩模和基板高的部分的衬垫层。
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公开(公告)号：KR1020010015338A
公开(公告)日：2001-02-26
申请号：KR1020000040544
申请日：2000-07-14
Applicant: 삼성전자주식회사
IPC: H01L21/3065
CPC classification number: H01L21/31144 , H01L21/31116 , H01L21/76802
Abstract: PURPOSE: A plasma etching method using a selective polymer deposition is to provide a high quality resolution and a good etching profile, by using a thin photoresist pattern as an etching mask. CONSTITUTION: An insulating layer on a wafer is plasma-etched for a predetermined interval of time by using a photoresist pattern(130) as a mask. A polymer layer(140) is formed by selectively evaporating polymer on the photoresist pattern. The insulating layer is plasma-etched by using the photoresist pattern and the polymer layer as a mask.
Abstract translation: 目的：使用选择性聚合物沉积的等离子体蚀刻方法是通过使用薄的光致抗蚀剂图案作为蚀刻掩模来提供高质量的分辨率和良好的蚀刻轮廓。 构成：通过使用光致抗蚀剂图案（130）作为掩模，在晶片上的绝缘层等离子体蚀刻预定的时间间隔。 通过在光致抗蚀剂图案上选择性地蒸发聚合物形成聚合物层（140）。 通过使用光致抗蚀剂图案和聚合物层作为掩模来对绝缘层进行等离子体蚀刻。
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Patent Agency Ranking
公开(公告)号：KR1020010010568A
公开(公告)日：2001-02-15
申请号：KR1019990029535
申请日：1999-07-21
Applicant: 삼성전자주식회사
IPC: C23C16/00
CPC classification number: H01L21/31116 , C09K13/00
Abstract: PURPOSE: Provided is a method of dry etching of an oxide film, which increases etching selection ratio to a nitride film by side product non-volatile and unstable and prevents global warming because decomposition is easy in the atmosphere by using fluorocarbon gas containing sulfur as an etching gas. CONSTITUTION: The method of dry etching of the oxide film using the nitride film as etching a barrier layer is characterized by providing the etching gas composed of fluorocarbon gas containing sulfur that is C4F8S, C3F6S, C3F6S2, hydrofluorocabon(HFC) containing sulfur or mixture thereof, and the etching gas can contain further oxygen, gas contained oxygen, a CxFy( x is integer of 1-6 and y is integer of 2-12) gas, a CxHyFz( x is integer 1-6, y is integer 1-4 and z is integer 2-10) gas, an inert gas or mixture thereof.
Abstract translation: 目的：提供一种干法蚀刻氧化膜的方法，其通过副产物非挥发性和不稳定的方式提高了氮化膜的蚀刻选择比，并且由于通过使用含硫的碳氟化合物气体在大气中容易分解而防止全球变暖 蚀刻气体。 构成：使用氮化物膜作为蚀刻阻挡层的氧化膜的干法蚀刻的方法的特征在于，提供由含有硫的碳氟化合物气体构成的蚀刻气体，所述硫是C4F8S，C3F6S，C3F6S2，含有硫的氢氟酸（HFC）或其混合物 ，并且蚀刻气体可以含有另外的氧，气体含有氧，C x F y（x为1〜6的整数，y为2〜12的整数），C x H y F z（x为1-6，y为整数1〜 4和z是2-10的整数）气体，惰性气体或其混合物。
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公开(公告)号：KR1019990071166A
公开(公告)日：1999-09-15
申请号：KR1019980006478
申请日：1998-02-27
Applicant: 삼성전자주식회사
IPC: H01L21/306
Abstract: 본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 2단계의 식각 공정으로 하부 물질층을 식각하는 반도체 소자 제조를 위한 식각 방법에 관한 것이다. 반도체 기판 상에 하부 물질층을 형성하고, 포토레지스트 패턴을 그 상부에 형성한다. 상기 하부 물질층을 포토레지스트 식각율에 대한 하부 물질층의 식각율의 비가 낮고, 식각 부산물이 상기 포토레지스트 패턴에 잘 흡착되지 않는 조건, 즉 플루오린에 비하여 카본의 비율이 낮은 식각 가스로 1차 식각한다. 1차 식각된 하부 물질층을 포토레지스트 식각율에 대한 하부 물질층의 식각율의 비가 높은 조건, 즉 플루오린에 비하여 카본의 비율이 높은 식각 가스로 2차 식각한다. 이때, 1차 식각 및 2차 식각은 하나의 챔버 내에서 순차적으로 행한한다 (인시튜 공정).
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公开(公告)号：KR1019970011157B1
公开(公告)日：1997-07-07
申请号：KR1019930013070
申请日：1993-07-12
Applicant: 삼성전자주식회사
Inventor： 안태혁
IPC: H01L27/10
Abstract: A semiconductor devices having a pad electrode which is divided to an active region and an unactive region is disclosed. The structure of pad electrode has different distance between electrodes. The distance of inter-electrodes passing the active region is different from the distance of the inter-electrodes passing the unactive region, such that the width of the electrode of the active region is wider than that of the width of the electrode of the inactive region. Also, the distance of electrode passing the active region has desired width of the semiconductor device.
Abstract translation: 公开了一种具有被划分为有源区和非活性区的焊盘电极的半导体器件。 焊盘电极的结构具有不同的电极距离。 通过有源区域的电极间距离不同于穿过非活性区域的电极的距离，使得有源区域的电极的宽度比非活性区域的电极的宽度宽 。 此外，通过有源区的电极的距离具有期望的半导体器件的宽度。
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公开(公告)号：KR1019950024257A
公开(公告)日：1995-08-21
申请号：KR1019940001364
申请日：1994-01-26
Applicant: 삼성전자주식회사
IPC: H01L21/302
Abstract: 제어부(43)로부터 인가되는 신호에 따라 램프 구동전원을 생성하여 출력하는 램프 전원공급부(42)와, 상기 랩프 전원공급부로부터 랩프 구동전원이 입력되면 동작됨으로써 자외선을 출력하는 자외선 광원(41)과, 상기 자외선 램프로부터 조사되는 자외선이 통과할 수 있는 자외선 투과창(46)이 형성되어 있으며, 상기 자외선에 의해 개스를 광여기시킴으로써 방전을 용이하게 하여 고주파 전력과의 정합특성을 개선시킨 플라즈마반응실(45)로 구성되어 있으며, 고주파 전력의 인가전 또는 동시에 반응챔버의 외부에 비치되어 있는 자외선 영역의 광원을 반응챔버 내부로 노출시킴으로써 자외선 빛에 의해 광여기된 자유전자의 작용으로 플라즈마 발생시 전력 부정합의 현상을 방지할수 있는 효과를 가진 저압/고밀도 플라즈마 발생장치에 관한 것.
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