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公开(公告)号：KR1020050047659A
公开(公告)日：2005-05-23
申请号：KR1020030081406
申请日：2003-11-18
Applicant: 삼성전자주식회사
Inventor： 안태혁
IPC: H01L21/335
Abstract: 리세스 채널 모오스 트렌지스터의 제조 방법이 개시되어 있다. 반도체 기판에 액티브 및 필드 영역을 정의한다. 상기 기판에서 채널 형성 영역에 불순물을 1차 주입한다. 상기 기판에서 게이트 형성 영역을 식각하여 게이트 트렌치를 형성한다. 상기 게이트 트렌치의 바닥면 아래에 선택적으로, 상기 1차 주입된 불순물과 동일한 타입의 불순물을 2차 주입한다. 상기 게이트 트렌치에서 채널이 형성되는 방향과 수직한 방향의 상기 액티브 양측 가장자리에, 상기 필드 영역의 경사에 의해 식각되지 않고 상기 필드 영역 측면에 잔류하는 반도체 기판을 제거한다. 이어서, 상기 게이트 트렌치에 게이트 산화막 및 게이트 도전막을 순차적으로 형성한다. 상기와 같이 게이트 트렌치 내에 불순물을 주입함으로서, 게이트 트렌치 깊이에 따른 문턱 전압 차이를 최소화할 수 있다.
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公开(公告)号：KR1020050028753A
公开(公告)日：2005-03-23
申请号：KR1020030065277
申请日：2003-09-19
Applicant: 삼성전자주식회사
IPC: H01L21/8242
Abstract: A semiconductor device having a cylindrical storage electrode is provided to effectively control a collapse of an electrode and avoid a bridge between adjacent electrodes by forming the lower region of a cylindrical storage node in an interlayer dielectric and by making a part of the lower region covered with an etch stop layer. An interlayer dielectric(110) is formed on a semiconductor substrate(100). The lower part of a contact hole penetrating the interlayer dielectric is filled with a recessed contact plug(120a) having a surface lower than the upper surface of the interlayer dielectric. An etch stop layer(140) is formed on the interlayer dielectric, having an opening positioned in the upper part of the contact hole wherein the width of the opening is smaller than that of the contact hole. The upper surface of the recessed contact plug, the sidewall of the contact hole and the sidewall of the opening are covered with a cylindrical storage node(150a) extending form the surface of the etch stop layer upward.
Abstract translation: 提供具有圆柱形存储电极的半导体器件，以有效地控制电极的塌陷，并且通过在层间电介质中形成圆柱形存储节点的下部区域并且通过使下部区域的一部分覆盖以避免相邻电极之间的桥接 蚀刻停止层。 在半导体衬底（100）上形成层间电介质（110）。 穿透层间电介质的接触孔的下部填充有表面低于层间电介质的上表面的凹陷接触塞（120a）。 在层间电介质上形成蚀刻停止层（140），其中开口位于接触孔的上部，其中开口的宽度小于接触孔的宽度。 凹形接触塞的上表面，接触孔的侧壁和开口的侧壁被从蚀刻停止层的表面向上延伸的圆柱形存储节点（150a）覆盖。
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公开(公告)号：KR1020050022617A
公开(公告)日：2005-03-08
申请号：KR1020030060198
申请日：2003-08-29
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: PURPOSE: A method of forming a recess trench for a recess channel MOSFET(Metal Oxide Semiconductor Field Effect Transistor) is provided to obtain quickly easily round upper and lower corners from the recess trench by using CDE(Chemical Dry Etching) or wet etching. CONSTITUTION: A pad oxide layer(120b) and a mask pattern are sequentially formed on a semiconductor substrate(100). A trench is formed in the resultant structure by etching selectively the pad oxide layer and the substrate using the mask pattern as an etching mask. A groove(135) for exposing an upper corner of the trench to the outside is formed on the pad oxide pattern. The exposed upper corner of the trench is roundly formed by performing CDE or wet etching thereon.
Abstract translation: 目的：提供一种形成用于凹槽沟道MOSFET（金属氧化物半导体场效应晶体管）的凹槽的方法，以通过使用CDE（化学干蚀刻）或湿式蚀刻从凹槽获得快速容易的圆形上下角。 构成：在半导体衬底（100）上依次形成衬垫氧化物层（120b）和掩模图案。 通过使用掩模图案选择性地蚀刻焊盘氧化物层和衬底作为蚀刻掩模，在所得结构中形成沟槽。 在衬垫氧化物图案上形成用于将沟槽的上角暴露于外部的凹槽（135）。 通过在其上进行CDE或湿蚀刻来圆形地形成沟槽的暴露的上角。
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公开(公告)号：KR100366620B1
公开(公告)日：2003-01-09
申请号：KR1020000033842
申请日：2000-06-20
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A semiconductor memory device having a self-aligned contact is provided to improve gap-fill capacity of a contact hole between bit lines, by self-aligning an opening for a storage node contact with a spacer after forming the spacer on a sidewall of a bit line pattern. CONSTITUTION: A plurality of gate electrodes are formed in a predetermined direction on a semiconductor substrate(1), separated from each other by a predetermined interval. The first insulating layer is formed on the resultant structure, and has at least the first and second openings exposing an active region of the substrate between the gate electrodes. The first and second conductive pad layers bury the first and second openings, respectively. The first interlayer dielectric(27) is formed on the first insulating layer having the first and second pad layers. A plurality of bit lines(29) are formed on the first interlayer dielectric in a direction perpendicular to the gate electrodes, penetrating the first interlayer dielectric to be electrically connected to the first pad layer. An insulating spacers are formed on both sidewalls of the bit lines. The second interlayer dielectric(35) is formed on the first interlayer dielectric having the bit lines and the insulating spacers. A storage electrode is self-aligned with the insulating spacer between the bit lines, penetrating the second and first interlayer dielectrics to be electrically connected to the second pad layer.
Abstract translation: 目的：提供一种具有自对准接触的半导体存储器件，通过在侧壁上形成间隔物之后，通过自对准用于存储节点接触的开口与间隔物来提高位线之间的接触孔的间隙填充容量 一个位线模式。 构成：多个栅电极在半导体衬底（1）上沿预定方向形成，并彼此隔开预定的间隔。 第一绝缘层形成在所得到的结构上，并且至少具有暴露栅电极之间的衬底的有源区的第一和第二开口。 第一和第二导电焊盘层分别掩埋第一和第二开口。 第一层间电介质（27）形成在具有第一和第二焊盘层的第一绝缘层上。 多个位线（29）在垂直于栅电极的方向上形成在第一层间电介质上，穿透第一层间电介质以电连接到第一焊盘层。 在位线的两个侧壁上形成绝缘间隔物。 第二层间电介质（35）形成在具有位线和绝缘间隔物的第一层间电介质上。 存储电极与位线之间的绝缘间隔物自对准，穿透第二和第一层间电介质以电连接到第二衬垫层。
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Patent Agency Ranking
公开(公告)号：KR100363710B1
公开(公告)日：2002-12-05
申请号：KR1020000048819
申请日：2000-08-23
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 셀프-얼라인 콘택을 갖는 반도체 장치 및 그 제조방법이 개시되어 있다. 상기 장치는, 반도체 기판과, 그 사이에 간격을 갖고 기판 상에 형성되며 제1 도전층 및 제1 도전층 상에 적층된 실리콘 질화막 마스크층을 포함하는 두 개의 도체 구조물들을 구비한다. 실리콘 질화막 마스크층의 상단보다 낮은 높이로 각 도체 구조물의 측면들 상에 실리콘 산화막 스페이서들이 형성된다. 각 도체 구조물의 측면들 및 실리콘 산화막 스페이서들의 표면 상에 실리콘 질화막 스페이서들이 형성된다. 도체 구조물들 및 기판 상에 실리콘 질화막 스페이서들을 노출시키고 각 도체 구조물의 위로 일부분 확장되는 셀프-얼라인 콘택홀을 갖는 실리콘 산화막으로 이루어진 절연층이 형성된다. 셀프-얼라인 콘택홀은 도체 구조물들에 셀프-얼라인되는 제2 도전층으로 매립된다. 도체 구조물의 측면들 상에 실리콘 산화막 스페이서 및 실리콘 질화막 스페이서로 구성된 듀얼 스페이서를 형성함으로써, 제1 도전층과 셀프-얼라인 콘택홀 내의 제2 도전층 간에 로딩 캐패시턴스를 감소시킬 수 있다.
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公开(公告)号：KR1020020042017A
公开(公告)日：2002-06-05
申请号：KR1020000071705
申请日：2000-11-29
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76802 , H01L21/31116 , H01L21/31144 , H01L21/76831
Abstract: PURPOSE: A semiconductor device manufacturing process is provided to prevent a damage of an upper portion of a contact hole due to a damage of sidewalls of a mask by forming the contact hole using a CH2F2 gas. CONSTITUTION: An oxide(19) is etched and a polymer(25) is simultaneously formed on an upper portion and sidewalls of a photoresist mask(21) by performing a plasma etch processing using a CH2F2 gas when forming a contact-type OCS(One Cylinder Storage) hole in order to form a micro-contact hole of a semiconductor device. Then, the oxide(19) is etched, while stopping the supply of the CH2F2 gas. In result, the polymer(25) deposited on the upper portion and sidewalls of the photoresist mask(21) prevent a damage of the contact hole due to a damage of the upper portion and sidewalls of the photoresist mask(21).
Abstract translation: 目的：提供一种半导体器件制造工艺，以通过使用CH2F2气体形成接触孔来防止由于掩模的侧壁的损坏而导致的接触孔的上部的损坏。 构成：蚀刻氧化物（19），并且当形成接触型OCS时，通过使用CH 2 F 2气体进行等离子体蚀刻处理，同时在光致抗蚀剂掩模（21）的上部和侧壁上形成聚合物（25） 气缸储存）孔，以形成半导体器件的微接触孔。 然后，在停止供给CH 2 F 2气体的同时蚀刻氧化物（19）。 结果，沉积在光致抗蚀剂掩模（21）的上部和侧壁上的聚合物（25）防止由于光致抗蚀剂掩模（21）的上部和侧壁的损坏而导致的接触孔的损坏。
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公开(公告)号：KR100338769B1
公开(公告)日：2002-05-30
申请号：KR1019990046631
申请日：1999-10-26
Applicant: 삼성전자주식회사
IPC: H01L21/311
CPC classification number: H01L21/31116
Abstract: 반도체장치의절연막식각방법을개시한다. 본발명의일 관점은반도체기판상에실리콘산화막또는실리콘질화막등의절연막을형성하고, CFO 가스등과같이 CHFO 가스이되상기 x는 0∼4의정수인가스를포함하는반응가스를이용하여절연막을건식식각한다. 이러한건식식각으로절연막을식각하여콘택홀(contact hole)을형성할수 있다.
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公开(公告)号：KR1020010037206A
公开(公告)日：2001-05-07
申请号：KR1019990044595
申请日：1999-10-14
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A method for manufacturing a capacitor is provided to prevent a leakage current phenomenon, by etching the second insulating layer by a dry etching method and eliminating an upper portion of the storage polysilicon layer by an etching method, thereby forming a round profile of the upper end portion of the storage polysilicon layer. CONSTITUTION: A polyplug(20) is formed on a semiconductor substrate(10). After a nitride layer stop layer and the first insulating layer are formed on the polyplug, the first insulating layer is patterned and etched until the polyplug is exposed, to form a storage hole. A storage polysilicon layer is formed inside the storage hole where the polyplug is exposed and along the surface of the first insulating layer. The second insulating layer is formed on the storage polysilicon layer. The second insulating layer is etched by a dry etching method and an upper portion of the storage polysilicon layer is etched away, so that the storage polysilicon layer outside the storage hole is etched and the storage polysilicon layer of a cylinder type is left. The second insulating layer inside the storage hole and the first insulating layer outside the storage hole are etched to form a storage electrode layer. A dielectric layer and a plate electrode layer are formed on the storage electrode layer.
Abstract translation: 目的：提供一种用于制造电容器的方法，通过用干蚀刻方法蚀刻第二绝缘层并通过蚀刻方法消除存储多晶硅层的上部，从而形成漏电流现象的圆形轮廓 存储多晶硅层的上端部分。 构成：在半导体衬底（10）上形成聚拢块（20）。 在氮化物层停止层和第一绝缘层形成在聚polyp条上之后，对第一绝缘层进行图案化和蚀刻，直到聚polyp条露出来形成存储孔。 在聚束块暴露的存储孔内部并且沿着第一绝缘层的表面形成存储多晶硅层。 第二绝缘层形成在存储多晶硅层上。 通过干蚀刻方法蚀刻第二绝缘层，并且蚀刻掉存储多晶硅层的上部，从而蚀刻存储孔外部的存储多晶硅层，并留下圆柱型存储多晶硅层。 在存储孔内部的第二绝缘层和存储孔外部的第一绝缘层被蚀刻以形成存储电极层。 电介质层和平板电极层形成在存储电极层上。
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公开(公告)号：KR1020010009084A
公开(公告)日：2001-02-05
申请号：KR1019990027250
申请日：1999-07-07
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a contact hole using a hard mask is provided to remove a hard mask without a damage on a semiconductor substrate. CONSTITUTION: A material layer is formed on a semiconductor substrate(1). A hard mask pattern(5a) is formed on the material layer. The material layer is etched by using the hard mask pattern as a mask. A contact hole for exposing a surface of the semiconductor substrate(1) is exposed by etching the material layer. A protective layer(7) with a superior etching selection ratio is formed within the contact hole. The hard mask pattern(5a) is removed. The protective layer(7) is removed.
Abstract translation: 目的：提供使用硬掩模形成接触孔的方法，以在半导体衬底上去除硬掩模而没有损坏。 构成：在半导体衬底（1）上形成材料层。 在材料层上形成硬掩模图案（5a）。 通过使用硬掩模图案作为掩模蚀刻材料层。 用于暴露半导体衬底（1）的表面的接触孔通过蚀刻该材料层而暴露。 在接触孔内形成具有优良蚀刻选择比的保护层（7）。 硬掩模图案（5a）被去除。 去除保护层（7）。
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