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公开(公告)号：KR1019920009453B1
公开(公告)日：1992-10-16
申请号：KR1019900021869
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The information searcher for the bus state analyzer can vary and define the quantity of the information searched and the condition of trigger. The searcher comprises basic unit modules (1-1n) for searching informations, and an integrating section (2) for integrating and multiplying logically the results of searched from the modules (1-1n), and generating the results.
Abstract translation: 总线状态分析器的信息搜索器可以变化并定义所搜索的信息的数量和触发条件。 搜索器包括用于搜索信息的基本单元模块（1-1n）和用于在逻辑上对从模块（1-1n）搜索的结果进行积分和乘积的积分部分（2），并且生成结果。
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公开(公告)号：KR1019920007945B1
公开(公告)日：1992-09-19
申请号：KR1019890019676
申请日：1989-12-27
Applicant: 한국전자통신연구원
IPC: G06F12/00
Abstract: The slot address designating method is to designating positions for slots of each system bus exclusively so that the processor boards inserted to the slots detects the position to which the boards are inserted. The position data for each processor board are assigned to signal pins of system bus (3) and the address designation or the interleaving sequence control is executed with priority.
Abstract translation: 插槽地址指定方法是专门为每个系统总线的时隙指定位置，以便插入插槽的处理器板检测插入板的位置。 每个处理器板的位置数据被分配给系统总线（3）的信号引脚，优先执行地址指定或交织序列控制。
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Patent Agency Ranking
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公开(公告)号：KR1019920003286B1
公开(公告)日：1992-04-27
申请号：KR1019890019673
申请日：1989-12-27
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: Synchronizing clock pulses are generated by a central slot (12) so as to be supplied through signal lines of a back plane (11). Two outer slots (13)(14) and (15)(16) which are adjacent to each other, and which are located outwardly from the central slot (12) are electrically bundled together as groups. The lengths of the signal lines of the back plane (11), which connect the groups to the central slot (12), are made to be the same, so that bus clocks of the central slot (12) should reach the groups simultaneously. The method simplifys the circuit constitution, to facilitate a serial termination, and minimizes the load of the signal receiving end.
Abstract translation: 同步时钟脉冲由中心槽（12）产生，以便通过背板（11）的信号线提供。 彼此相邻并从中心狭槽（12）向外定位的两个外槽（13）（14）和（15）（16）被组合在一起。 将组合到中心狭槽（12）的背板（11）的信号线的长度相同，使得中心槽（12）的总线时钟同时到达组。 该方法简化了电路结构，便于串行终端，并使信号接收端的负载最小化。
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公开(公告)号：KR1019920000480B1
公开(公告)日：1992-01-14
申请号：KR1019890019308
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/32
Abstract: The method is to support interprocess communication of multiprocessor system. When an interrupt request signal is received, arbiters are drived fromthe first bit according to thepriorities to allow the usage of interrupt bus for processors. The circuit includes an interrupt requester (5) for request arbitration to interrupt handlers (3,4) when the interrupt request signal from processors (1,2) is received, interrupt handlers (3,4) for processing the arbitration request and interrupts occured in boards in which processors are deposited, an interrupt arbiter (7) for executing the arbitration and sending the result to the interrupt requestor (5), and for arbitrating the interrupt handlers, and an interrupt bus synchronizing signal (IBSYNC) driver (8) for generating the IBSYNC signal to drive the signal line (9) and for sending the IBSYNC signal to the interrupt requester (5).
Abstract translation: 该方法是支持多处理器系统的进程间通信。 当接收到中断请求信号时，根据优先级从第一位驱动仲裁器，以允许对处理器使用中断总线。 当接收到来自处理器（1,2）的中断请求信号时，该电路包括用于请求仲裁以中断处理程序（3,4）的中断请求器（5），用于处理仲裁请求的中断处理程序（3,4） 在处理器存放的板中，执行仲裁并将结果发送给中断请求者（5）并用于仲裁中断处理程序的中断仲裁器（7）和中断总线同步信号（IBSYNC）驱动器（8） 用于产生IBSYNC信号以驱动信号线（9）并将IBSYNC信号发送到中断请求器（5）。
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