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公开(公告)号：KR1019940008484B1
公开(公告)日：1994-09-15
申请号：KR1019910023201
申请日：1991-12-17
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The method minimizes data response time consuming to refer data from memory using data transfer ReQuester (RQ) and data transfer bus ResPonder (RP). The method is arranged that: multiple data transfer bus requesters (RQ1-RQn) and multiple data transfer bus responders (RP1-RPn) use for shared data transfer bus to support arbitration bus; data transfer executed by RQs and RPs is synchronized with a bus clock; a memory reference (read or write) request by processors (P1-Pn) happens between data transfer bus requesters (RQ1-RQn) and data transfer bus responders (RP1-RPn).
Abstract translation: 该方法使用数据传输ReQuester（RQ）和数据传输总线ResPonder（RP）来最大限度地减少从存储器引用数据的数据响应时间。 该方法的安排是：多个数据传输总线请求者（RQ1-RQn）和多个数据传输总线应答器（RP1-RPn）用于共享数据传输总线以支持仲裁总线; 由RQ和RP执行的数据传输与总线时钟同步; 在数据传输总线请求器（RQ1-RQn）和数据传输总线响应器（RP1-RPn）之间发生处理器（P1-Pn）的存储器引用（读或写）请求。
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公开(公告)号：KR1019930007019B1
公开(公告)日：1993-07-26
申请号：KR1019900021857
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The bus state analyzer debugs a multiprocessor system which adapts synchronous pended transmission type. The bus state analyzer includes a bus timing control signal generator (2) for generating timing control signal of buses, a bus interface unit (1) for receiving data from system bus according to timing control signal, a bus data search unit (3) for comparing bus data of the bus interface unit (1) and internal bus data, a function controller (4) for generating bus control signal according to bus clock signal and data coincide signal transmitted from the bus data search unit (3), a data memory (5) for storing input data of the bus interface unit on a data area which is determined by a control signal transmitted from the function controller, and processor unit (6) for controlling analyzing process.
Abstract translation: 总线状态分析器调试适应同步倾斜传输类型的多处理器系统。 总线状态分析器包括用于产生总线定时控制信号的总线定时控制信号发生器（2），用于根据定时控制信号从系统总线接收数据的总线接口单元（1），总线数据搜索单元 比较总线接口单元（1）和内部总线数据的总线数据，根据总线时钟信号和从总线数据搜索单元（3）发送的数据重合信号产生总线控制信号的功能控制器（4），数据存储器 （5），用于将总线接口单元的输入数据存储在由功能控制器发送的控制信号确定的数据区域上，以及用于控制分析处理的处理器单元（6）。
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Patent Agency Ranking
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公开(公告)号：KR1019920009453B1
公开(公告)日：1992-10-16
申请号：KR1019900021869
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The information searcher for the bus state analyzer can vary and define the quantity of the information searched and the condition of trigger. The searcher comprises basic unit modules (1-1n) for searching informations, and an integrating section (2) for integrating and multiplying logically the results of searched from the modules (1-1n), and generating the results.
Abstract translation: 总线状态分析器的信息搜索器可以变化并定义所搜索的信息的数量和触发条件。 搜索器包括用于搜索信息的基本单元模块（1-1n）和用于在逻辑上对从模块（1-1n）搜索的结果进行积分和乘积的积分部分（2），并且生成结果。
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