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公开(公告)号：KR101127962B1
公开(公告)日：2012-03-26
申请号：KR1020080131607
申请日：2008-12-22
Applicant: 한국전자통신연구원
CPC classification number: G09G5/39 , G09G2360/123 , G09G2360/128 , H04N19/423
Abstract: A method for managing a frame memory includes: determining a frame memory structure with reference to memory configuration information and image processing information; configuring a frame memory such that a plurality of image signals are stored in each page according to the frame memory structure; and computing a signal storage address by combining image acquiring information by bits, and accessing a frame memory map to write or read an image signal by pages.
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公开(公告)号：KR1020100073029A
公开(公告)日：2010-07-01
申请号：KR1020080131607
申请日：2008-12-22
Applicant: 한국전자통신연구원
CPC classification number: G09G5/39 , G09G2360/123 , G09G2360/128 , H04N19/423
Abstract: PURPOSE: An image processing apparatus and a frame managing method for the same are provided to efficiently support an interlace scanning by changing a line distance and accessing to selected frame/field in each macro block. CONSTITUTION: A host interface bus(110) transfers initializing information and image data stream for each functional module from a host system(200). A stream(121) acquires and buffers the image data stream and provides the image data stream to a stream controller(122). The stream controller interprets the image data stream and distributes data.
Abstract translation: 目的：提供一种用于其的图像处理装置和帧管理方法，以通过改变行距离和访问每个宏块中所选择的帧/场来有效地支持隔行扫描。 构成：主机接口总线（110）从主机系统（200）传送每个功能模块的初始化信息和图像数据流。 流（121）获取并缓冲图像数据流，并将图像数据流提供给流控制器（122）。 流控制器解释图像数据流并分发数据。
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Patent Agency Ranking
公开(公告)号：KR100928701B1
公开(公告)日：2009-11-27
申请号：KR1020070132721
申请日：2007-12-17
Applicant: 한국전자통신연구원
Abstract: An intra prediction coding acceleration method and a device thereof are provided to accelerate an intra prediction coding process by using a fast mode decision method for intra prediction. An intra prediction mode unit calculates an intra prediction mode according to neighboring block data of a block for performing intra prediction. A DCT(Discrete Cosine Transform) converter converts the calculated intra prediction mode value through a DCT process. An SAE(Sum of Absolute Error) calculator(600) calculates an SAE value according to the DCT value. A quantizer quantizes the DCT-applied value. An output multiplexer determines an optimum quantized intra mode by using the SAE calculated value and the quantized value.
Abstract translation: 提供帧内预测编码加速方法及其装置，以通过使用用于帧内预测的快速模式判定方法来加速帧内预测编码处理。 帧内预测模式单元根据用于执行帧内预测的块的相邻块数据来计算帧内预测模式。 DCT（离散余弦变换）转换器通过DCT处理将计算的帧内预测模式值转换。 SAE（绝对误差和）计算器（600）根据DCT值计算SAE值。 量化器量化DCT应用的值。 输出多路复用器通过使用SAE计算值和量化值来确定最佳量化帧内模式。
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公开(公告)号：KR100928272B1
公开(公告)日：2009-11-24
申请号：KR1020070132717
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: H04N19/433
Abstract: 본 발명은 현재 프레임의 매크로 블록에서 홀수 행만을 저장하는 CME 매크로 블록 버퍼, 현재 프레임의 매크로 블록에 상응하는 참조 프레임의 휘도 신호의 홀수 행만을 저장하는 CME 참조 영역 버퍼 및 상기 CME 매크로 블록 버퍼 및 상기 CME 참조 영역 버퍼에 저장된 값에 상응하여 2 화소 추정을 수행하는 2화소 추정부를 포함하는 동영상 부호화에서 움직임 추정 장치를 제공할 수 있다.
H.264, 움직임 추정Abstract translation: 当在对H.254视频进行编码的同时执行运动估计时，提供了用于视频编码的运动估计方法及其设备，以有效地使用存储器。 CME（粗略模式估计）宏块缓冲器（223）仅在当前帧的宏块中存储奇数单元行。 CME参考区缓冲器（221）仅存储对应于当前帧的宏块的参考帧的亮度信号的奇数单元行。 2像素估计器（225）根据存储在CME宏块缓冲器和CME参考区域缓冲器中的值执行2像素估计处理。 CME宏块缓冲区包括如下。 第一个CME宏块缓冲区只存储奇数行。 第二个CME宏块缓冲区只存储偶数行。
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公开(公告)号：KR1020090065243A
公开(公告)日：2009-06-22
申请号：KR1020070132721
申请日：2007-12-17
Applicant: 한국전자통신연구원
CPC classification number: H04N19/159 , H04N19/103 , H04N19/124 , H04N19/625
Abstract: An intra prediction coding acceleration method and a device thereof are provided to accelerate an intra prediction coding process by using a fast mode decision method for intra prediction. An intra prediction mode unit calculates an intra prediction mode according to neighboring block data of a block for performing intra prediction. A DCT(Discrete Cosine Transform) converter converts the calculated intra prediction mode value through a DCT process. An SAE(Sum of Absolute Error) calculator(600) calculates an SAE value according to the DCT value. A quantizer quantizes the DCT-applied value. An output multiplexer determines an optimum quantized intra mode by using the SAE calculated value and the quantized value.
Abstract translation: 提供帧内预测编码加速方法及其装置，以通过使用用于帧内预测的快速模式判定方法来加速帧内预测编码处理。 帧内预测模式单元根据用于执行帧内预测的块的相邻块数据来计算帧内预测模式。 DCT（离散余弦变换）转换器通过DCT处理转换计算出的帧内预测模式值。 SAE（绝对误差和）计算器（600）根据DCT值计算SAE值。 量化器量化DCT应用值。 输出多路复用器通过使用SAE计算值和量化值来确定最佳量化帧内模式。
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公开(公告)号：KR1020090039603A
公开(公告)日：2009-04-22
申请号：KR1020080089241
申请日：2008-09-10
Applicant: 한국전자통신연구원
IPC: H04N19/436
CPC classification number: H04N19/436 , H04N19/117 , H04N19/13 , H04N19/139 , H04N19/176
Abstract: An apparatus and a method for video encoding using a pipeline method having variable time slot are provided to prevent a delay of a performing time and unnecessary electrical power consumption by regulating a length of a time slot according to a performing time of a video encoding step by using a termination signal generated in a function block. A video input module(301) receives a digital image signal from an external device, and stores the received signal to a frame memory(308) in macro block unit, and a vertical synchronizing signal, a horizontal synchronization signal, and a data bus signal of a video signal are received and delivered to each of function blocks. A controller(302) determines a length of a time slot according to a termination signal of function blocks(303,304,305,306,307) which are performing a video encoding step. And the controller generates a start signal to operate each of the function blocks according to a determined time slot.
Abstract translation: 提供一种使用具有可变时隙的流水线方法进行视频编码的装置和方法，以通过根据视频编码步骤的执行时间调节时隙的长度来防止执行时间的延迟和不必要的电力消耗 使用在功能块中生成的终止信号。 视频输入模块（301）从外部设备接收数字图像信号，并以宏块单位将接收到的信号存储到帧存储器（308），以及垂直同步信号，水平同步信号和数据总线信号 的视频信号被接收并传送到每个功能块。 控制器（302）根据执行视频编码步骤的功能块（303,304,305,306,307）的终止信号来确定时隙的长度。 并且控制器根据确定的时隙产生启动信号以操作每个功能块。
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公开(公告)号：KR1020080042020A
公开(公告)日：2008-05-14
申请号：KR1020070113572
申请日：2007-11-08
Applicant: 한국전자통신연구원
IPC: G06F17/50
CPC classification number: G06F11/3668 , G06F11/3457
Abstract: An integrated simulation method of a video codec implemented by software and hardware is provided to simulate various input video and verify a result according to a standard mode defined in a flow chart by combining software and hardware codecs variously while changing codec parameters for the input videos when the hardware codec is developed based on the software codec. Entire work(411) for simulation is divided into unit works arranged in sequence of a flow chart(421), and the unit works are defined into a connection node(422,423) performed with relation between the unit works, an independent node(424,425) performed independently without any relation, and a lower node guiding a lower hierarchical structure. The lower node is represented as a lower flow chart(431) having a few of hierarchical structures linked with the flow chart, and each unit work used in the lower flow chart is defined again into the connection, independent, and lower nodes according to relation, independency, and level. The simulation is performed according to a work flow formed by the defined nodes. A state value of the connection node is changed in real-time by connecting to work execution.
Abstract translation: 提供由软件和硬件实现的视频编解码器的集成仿真方法，用于通过在改变输入视频的编解码器参数的同时组合软件和硬件编解码器来根据流程图中定义的标准模式来模拟各种输入视频并验证结果， 硬件编解码器是基于软件编解码器开发的。 用于仿真的整个工作（411）被划分为以流程图（421）顺序排列的单元工作，并且单元工作被定义为与单元作品之间的关系执行的连接节点（422,423），独立节点（424,425） 独立执行，没有任何关系，下层节点引导较低层次结构。 下部节点表示为具有与流程图链接的几个层次结构的下部流程图（431），并且根据关系再次将下游流程图中使用的每个单位工作定义为连接，独立和下部节点 ，独立性和水平。 根据由定义的节点形成的工作流程进行模拟。 通过连接到工作执行，实时更改连接节点的状态值。
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