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    61.
    发明专利
    未知

    公开(公告)号：DE69808950T2

    公开(公告)日：2003-12-24

    申请号：DE69808950

    申请日：1998-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIBELLINO CALOGERO ,  MILAZZO PATRIZIA ,  PULVIRENTI FRANCESCO

    IPC: H03K4/02 ,  H03K17/16

    Abstract: Integrated circuit (20, 80, 90) generating at least a voltage linear ramp having a slow rise of the type comprising an input terminal (21, 81, 91), connected to a first voltage reference (VREF) and an output terminal (24, 84, 94) adapted for providing a controlled ramp signal (VRAMP), the circuit comprising at least one operational amplifier (OP3) having a non-inverting input terminal connected to said input terminal (21, 81, 91) and to an output terminal in feedback on an inverting input terminal and connected to the output terminal (24, 84, 94) of the ramp generator circuit (20, 80, 90) itself. The ramp voltage generator (20, 80, 90) according to the invention further comprises a first storage capacitance (Cs) connected between the non-inverting input terminal of the operational amplifier (OP3) and a ground voltage reference (GND) and loaded by means of a second pumping capacitance (Cp) inserted in parallel to said first capacitance (Cs) between the input terminal (21, 81, 91) of the ramp generator circuit (20, 80, 90) and the ground voltage reference (GND).

    63.
    发明专利
    未知

    公开(公告)号：ITMI982003A1

    公开(公告)日：2000-03-14

    申请号：ITMI982003

    申请日：1998-09-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PULVIRENTI FRANCESCO ,  RAVANELLI ENRICO

    IPC: H01L27/02 ,  H01L27/092

    Abstract: The present invention relates to a circuit device for protection against electrostatic discharge, and being immune to the latch-up phenomenon. The circuit device is of the integrated type in a portion of a semiconductor integrated circuit. The device includes an active limiting element and a resistor connected in series between a terminal of the active element connected to an input/output pin of the integrated circuit, and a terminal of a circuit to be protected. The active element is a bipolar transistor having a base terminal and an emitter-acting collector terminal connected together. The distributed resistor is formed in an emitter-acting collector region of the transistor which is diffused and elongated at the surface inside a base pocket of the transistor.

    Treiberschaltung, entsprechende integrierte Schaltung und Vorrichtung
    66.
    发明专利
    Treiberschaltung, entsprechende integrierte Schaltung und Vorrichtung 未知

    公开(公告)号：DE102016109333A1

    公开(公告)日：2017-05-18

    申请号：DE102016109333

    申请日：2016-05-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PULVIRENTI FRANCESCO ,  CAGGEGI GIOVANNI ,  PALUMBO VINCENZO ,  CANTONE GIUSEPPE

    IPC: H03K17/06

    Abstract: Schaltung zum Vorsehen eines Hochspannungsleiterpfades der Art einer Diode mit niedrigem Spannungsabfall zwischen einem Gleichspannungsversorgungsanschluss (VCC) und einem Bootstrap-Anschluss (BOOT) beim Laden eines Versorgungskondensators (CB) zum Treiben (HS_DRV) eines Leistungsschalters (PW1), wobei der Kondensator (CB) zwischen dem Bootstrap-Anschluss (BOOT) und einem Ausgangsanschluss (OUT) angeordnet ist, der alternativ zwischen einer Niederspannung (GND) und einer Hochspannungs-Gleichspannung (HV rail) schaltbar ist (PW2). In einer Ausführungsform weist die Schaltung einen ersten (LD1) und einen zweiten (LD2) Transistor, wie z. B. LDMOS-Verarmungstransistoren, auf, wobei der erste (LD1) Transistor in einer Kaskoden-Anordnung zwischen dem Bootstrap-Anschluss (BOOT) und dem Gleichspannungsversorgungsanschluss (VCC) angeordnet ist und der zweite Transistor (LD2) mit einem Messkomparator (CMP) zum Vergleichen der Spannung an dem Bootstrap-Anschluss (BOOT) mit der Spannung an dem Gleichspannungsversorgungsanschluss (VCC) gekoppelt ist. Der erste (LD1) und der zweite (LD2) Transistor haben gemeinsame mit dem Gleichspannungsversorgungsanschluss (VCC) gekoppelte Steueranschlüsse (G) und gemeinsame Kopplungsanschlüsse (D) zu dem Bootstrap-Anschluss (BOOT).

    67.
    发明专利
    未知

    公开(公告)号：DE60035113T2

    公开(公告)日：2008-02-07

    申请号：DE60035113

    申请日：2000-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SIGNORELLI TIZIANA ,  PULVIRENTI FRANCESCO ,  RIBELLINO CALOGERO

    IPC: G01R31/30 ,  G06F11/00

    Abstract: The invention relates to a circuit architecture and a relevant method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture of this invention comprises at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a means (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from the normal mode over to the trimming mode. This circuit architecture further comprises a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing up the non-volatile memory (3) state at power-on or at the simulating phase, and storing up the sequence (25) of trimming data at the programming phase; an interface (6) is provided between said pins (7,8,9) and the memory unit (2,3) for initially storing the data sequence (25) into the volatile memory unit and subsequently timing the trimming operation.

    68.
    发明专利
    未知

    公开(公告)号：DE60035113D1

    公开(公告)日：2007-07-19

    申请号：DE60035113

    申请日：2000-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SIGNORELLI TIZIANA ,  PULVIRENTI FRANCESCO ,  RIBELLINO CALOGERO

    IPC: G01R31/30 ,  G06F11/00

    Abstract: The invention relates to a circuit architecture and a relevant method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture of this invention comprises at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a means (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from the normal mode over to the trimming mode. This circuit architecture further comprises a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing up the non-volatile memory (3) state at power-on or at the simulating phase, and storing up the sequence (25) of trimming data at the programming phase; an interface (6) is provided between said pins (7,8,9) and the memory unit (2,3) for initially storing the data sequence (25) into the volatile memory unit and subsequently timing the trimming operation.

    70.
    发明专利
    未知

    公开(公告)号：DE60019255D1

    公开(公告)日：2005-05-12

    申请号：DE60019255

    申请日：2000-01-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PULVIRENTI FRANCESCO

    IPC: G01R31/317 ,  G11C17/18 ,  H01L21/66 ,  H03K17/693

    Abstract: The invention relates to a method and a circuit for carrying out a trimming operation on integrated circuits (2) having a trimming circuit portion (1) which includes memory elements (10) and a means (8) of modifying the state of said memory elements (10), at least a first input or supply pin (IN), an output pin (OUT), and a second supply pin (GND). The method comprises the following steps: enabling a single pin (OUT) to receive trimming data by biasing the pin to outside its operating range; to acquire such data, obtaining a clock signal from a division of the bias potential of the trimming pin (OUT); obtaining the logic value of the trimming data from a different division of the bias potential of said pin (OUT); enabling serial acquisition of the data according to the clock signal; and transferring the data to the means (8) of modifying the state of the memory elements (10). Advantageously, the data are also transferred into a selection logic (11), by-passing the means (8) for modifying the state of the memory elements (10), on the occurrence of a simulated trimming operation.

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