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    TURN-OFF CIRCUIT FOR LDMOS WHEN REVERSE CURRENT EXISTS
    1.
    发明专利
    TURN-OFF CIRCUIT FOR LDMOS WHEN REVERSE CURRENT EXISTS 失效

    公开(公告)号：JPH1174769A

    公开(公告)日：1999-03-16

    申请号：JP17734198

    申请日：1998-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GENOVA ANGELO ,  GARIBOLDI ROBERTO

    IPC: H03K17/06 ,  H03K17/08

    Abstract: PROBLEM TO BE SOLVED: To automatically switch off an LDMOS transistor by having a zener diode which is biased forward between a supply node and a source node of an LDMOS transistor and providing a 2nd zener diode in place of a charging diode. SOLUTION: A 1st Zener diode Z1 is used in place of a charging diode of a capacity Cp which exists at Vs supply voltage. A 2nd Zener diode Z2 is connected between a source node S of a transistor LD and the supply node Vs. When Zehner voltages VZ1 and VZ2 of the diodes Z1 and Z2 satisfy the condition Vs>VZ1, there holds VTH>VZ1-VZ2, and when Vs Vs+ Vbe-VZ2 holds. VTH is the threshold voltage of the transistor LD, and the difference between the source voltage of the transistor LD and the substrate voltage is equal to VZ2-nVbe.

    INTEGRATED DEVICE FOR SWITCHING SYSTEM PROVIDED WITH FILTERED REFERENCE AMOUNT
    2.
    发明专利
    INTEGRATED DEVICE FOR SWITCHING SYSTEM PROVIDED WITH FILTERED REFERENCE AMOUNT 失效

    公开(公告)号：JPH11168369A

    公开(公告)日：1999-06-22

    申请号：JP19477998

    申请日：1998-07-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GENOVA ANGELO ,  CANTONE GIUSEPPE ,  GARIBOLDI ROBERTO

    IPC: H03K5/08 ,  G05F3/26 ,  H03K17/16

    Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive integrated device of relatively simple and compact constitution without receiving interference at the time of switching. SOLUTION: In this integrated device 105 for a switching system provided with a control means 110 for generating switching control signals, a reference means 120 for generating a reference amount Qref and a means 110 for using the reference amount, the means 130 for storing the reference amount, a switch means 122 for connecting the reference means 120 to a using means 110 and a storage means 130 so as to supply the reference amount Qref in a first operation state and interrupting the reference means 120 from the using means 110, connecting the storage means 130 to the using means 110 and supplying the stored reference amount Qref in a second operation state and a filter means 135 for maintaining the switch means 122 in the second operation sate during a filtering period corresponding to the switching of control signals Sh are provided.

    PROTECTION CIRCUIT FOR CONTROLLING GATE VOLTAGE OF HVLDMOS TRANSISTOR
    3.
    发明专利
    PROTECTION CIRCUIT FOR CONTROLLING GATE VOLTAGE OF HVLDMOS TRANSISTOR 失效

    公开(公告)号：JPH1168531A

    公开(公告)日：1999-03-09

    申请号：JP17718598

    申请日：1998-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GENOVA ANGELO ,  GARIBOLDI ROBERTO

    IPC: H03K17/06 ,  H03K17/0812 ,  H03K17/16

    Abstract: PROBLEM TO BE SOLVED: To surely control a gate voltage so that an LDMOS transistor can not be switched on undesiredly by providing a 2nd inverter provided with an input end, to which a 2nd logical signal is inputted and an output end which is connected to a gate node of the LDMOS transistor. SOLUTION: In a pMOS transistor M1, its source is connected to the cathode of a diode D1 and to a charging terminal of a bootstrap capacitor Cp, also its drain is connected to the drain of an nMOS transistor M2 and to the gate of an LDMOS integrated transistor LD. The source of the transistor M2 is connected to an output node A of a control inverter 101 and to the other terminal of the condenser Cp. Then gates of the transistors M1 and M2 are controlled by a logical signal UVLOb and prevent the transistor LD from being turned on accidentally.

    METHOD FOR CONTROLLING VOLTAGE OF HVLDMOS CIRCUIT BOARD
    4.
    发明专利
    METHOD FOR CONTROLLING VOLTAGE OF HVLDMOS CIRCUIT BOARD 失效

    公开(公告)号：JPH1168530A

    公开(公告)日：1999-03-09

    申请号：JP17706298

    申请日：1998-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GENOVA ANGELO ,  TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GARIBOLDI ROBERTO

    IPC: H03K17/06

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit, capable of more efficiently charging a capacitance without increasing the power consumption for a parasitic transistor. SOLUTION: A circuit that charges a capacitance C with an LDMOS-LD integrated transistor is provided with a switching means SWb controlled by a logical signal UVLO. Hereby, the switching means SWb is made into active state, in order to charge a board node with the current whose maximum value is restricted to the pre-established value during a phase, in which a supply voltage Vs of an integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit.

    5.
    发明专利
    未知

    公开(公告)号：ITUB20155707A1

    公开(公告)日：2017-05-18

    申请号：ITUB20155707

    申请日：2015-11-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAGGEGI GIOVANNI ,  PULVIRENTI FRANCESCO ,  CANTONE GIUSEPPE ,  PALUMBO VINCENZO

    IPC: H03K17/06

    Abstract: A circuit provides a high-voltage low-drop diode-like conductive path between a DC voltage supply terminal and a bootstrap terminal in charging a supply capacitor for driving a power switch with the capacitor set between the bootstrap terminal and an output terminal alternatively switchable between a low voltage and a high voltage DC voltage. In an embodiment, the circuit includes first and second transistors such as LDMOS depletion transistors with the first transistor set in a cascode arrangement between the bootstrap terminal and the DC voltage supply terminal and the second transistor coupled with a sense comparator for comparing the voltage at the bootstrap terminal with the voltage at said DC voltage supply terminal. The first and second transistors have common control terminals coupled with the DC voltage supply terminal and common coupling terminals to the bootstrap terminal.

    7.
    发明专利
    未知

    公开(公告)号：DE602006009422D1

    公开(公告)日：2009-11-05

    申请号：DE602006009422

    申请日：2006-03-17

    Applicant: ST MICROELECTRONICS SRL ,  DORA SPA

    Inventor： CAPPELLETTI ROBERTO ,  CANTONE GIUSEPPE ,  ANTONELLI BARBARA ,  CASTIGLIOLA ANTONELLO ,  LASCIANDARE ALESSANDRO ,  MARANO VINCENZO

    IPC: H04B3/54

    Abstract: An electronic synchronous/asynchronous transceiver device for power line communication networks is integrated into a single chip and operates from a single supply voltage. The transceiver device includes: at least an internal register that is programmable through a synchronous serial interface; at least a line driver for a two-way network communication over power lines implemented by a single ended power amplifier with direct accessible input and output lines that is part of a tunable active filter for the transmission path; and at least a couple of linear regulators for powering with different voltage levels different kind of external controllers linked to the transceiver device.

    8.
    发明专利
    未知

    公开(公告)号：DE69530288D1

    公开(公告)日：2003-05-15

    申请号：DE69530288

    申请日：1995-05-31

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： CANTONE GIUSEPPE ,  NOVELLI ALDO

    IPC: H03K5/1532 ,  H03K5/1252 ,  H03K5/01 ,  H03K5/153

    Abstract: The present invention relates primarily to a pulse generator (GEN) having an input (ID) and two outputs (OR,OS) at which to generate respectively a pulse in relation to a edge of a different type at input. The generator provides two distinct logic circuit blocks of the sequential type hence mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks (G3,G4) it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

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