公开(公告)号：DE10007176A1

公开(公告)日：2001-08-30

申请号：DE10007176

申请日：2000-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT

IPC: G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  H03K17/14 ,  H03K17/693

Abstract: A decoding apparatus for transmitting a high voltage signal includes a final decoder for switchably transmitting a transmission signal. The final decoder has a switching device that has at least one depletion-mode-type field effect transistor and/or field effect transistor having a low threshold voltage (i.e., 0.1 to 0.4 V), in particular, a low VT field effect transistor. A transmission signal line supplies the transmission signal to the decoder, a driver signal line supplies a driver signal to the decoder, and an output signal line outputs an output signal from the decoder. The driver signal line applies the driver signal to the gate line, the transmission signal line applies the transmission signal to the source line. The field effect transistor is configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal. The configuration reduces the likelihood of channel degradation and of failure in the field effect transistor.

公开(公告)号：DE10108744B4

公开(公告)日：2008-03-20

申请号：DE10108744

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  CHRYSOTOMINDES ATHANASIA

IPC: G11C11/407 ,  G11C7/06 ,  G11C7/12 ,  H01L27/02 ,  H01L27/108

Abstract: The integrated DRAM memory module has sense amplifiers which are each formed, in the integrated module, from a multiplicity of transistor structures that are arranged regularly in cell arrays and include amplification transistors for bit line signal amplification. The amplification transistors lie opposite one another in pairs, are structurally identical, and are arranged equally spaced apart in rows. Voltage equalization transistors ensure voltage equalization between sense amplifier drive signals. The cell array order provides for each row with amplification transistors situated in a structurally identical transistor environment to be interrupted in a predetermined period by voltage equalization transistors. The structure of the voltage equalization transistors in a region of proximity to the adjoining amplification transistors is adapted to the structure thereof, and the voltage equalization transistors are at the same distance from the mutually adjoining amplification transistors as the amplification transistors of the same row are from one another.

公开(公告)号：DE102006024215A1

公开(公告)日：2007-10-31

申请号：DE102006024215

申请日：2006-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  FISCHER HELMUT

IPC: G11C29/52 ,  G06F11/00 ,  G06F12/04

Abstract: The method involves simultaneously selecting a number of data bits corresponding to a data item width from memory cells (1) of a cell field (2) of a semiconductor memory device, where the selected data bits are combined in groups on a data bus with another data item width that is small when compared to the former data item width. The data bits are temporally outputted in a distributed manner to several successive edges of a clock signal, where bit lines of memory cells are activated by a common column select line. An independent claim is also included for a semiconductor memory device with a cell field.

公开(公告)号：DE10219652B4

公开(公告)日：2007-01-11

申请号：DE10219652

申请日：2002-05-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT

IPC: G11C11/407 ,  G11C7/22

Abstract: The first clock reception circuit (12) receives first external clock signal and generates first internal clock signal for use in the memory circuit. There is a second clock reception circuit (14) with the same characteristics as the first clock reception circuit. The second clock reception cirucit has lower current consumption than the first circuit. There is a switch block (16), operating according to both internal clock signals and switching-off the first clock reception circuit, if the power-down-precharge-mode is used. The switch block operates according to second internal clock signal, when the first circuit is off. Independent claim is included for operational method of invented memory circuit.

公开(公告)号：DE50109730D1

公开(公告)日：2006-06-14

申请号：DE50109730

申请日：2001-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  MUELLER JOCHEN

IPC: H01L23/525

Abstract: The invention relates to a fusible link configuration in or on integrated circuits, in particular highly integrated memory chips, in which in each case one bank of fusible links (F1, F2, . . . ), together with an evaluation logic unit is configured beside and in association with a memory field segment. The evaluation logic unit is electrically connected to the fusible links (F1, F2, . . . ) and determines whether one or more of the fusible links (F1, F2, . . . ) is severed. One or more banks of the fusible links (F1, F2, . . . ) are divided up into smaller units while restricting the width(s) of the bank or banks. The units are grouped such that at least some of the fusible links (F1, F2, . . . ) are located beside one another transversely with respect to the width direction of the bank.

公开(公告)号：DE102004058220A1

公开(公告)日：2006-06-01

申请号：DE102004058220

申请日：2004-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCKE PAUL ,  FISCHER HELMUT

IPC: G11C7/10 ,  G11C7/04 ,  G11C11/4093

Abstract: A memory/storage module (10) and output driver (30) which for outputting the data stored in at least one memory cell generates an output signal (DQ). The output driver circuit (30) has at least one control terminal (S30a,b), via which the rise and fall rate of the rising and falling flanks of the output signal (DQ) is influenced by a control signal (ST1,ST2) present at the control terminal (S30a,b). An independent claim is included for a method for driving a memory/storage module.

公开(公告)号：DE102004049194B3

公开(公告)日：2006-02-02

申请号：DE102004049194

申请日：2004-10-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  BRUCKE PAUL

IPC: G11C7/10 ,  H03K19/003 ,  H03K19/0185

公开(公告)号：DE10315528A1

公开(公告)日：2004-11-11

申请号：DE10315528

申请日：2003-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNUEPFER BERNHARD ,  FISCHER HELMUT

IPC: G11C7/10 ,  G11C11/4093 ,  G11C7/22 ,  G11C11/407

Abstract: A data memory circuit (10) comprises addressable memory cells (11), an external command decoder (13) and an operation control unit (12). A decision unit recognizes any inadmissible commands and a command buffer (50.1-n) release commands which were received during the inadmissible period at the end of this period.

公开(公告)号：DE10232962A1

公开(公告)日：2004-02-19

申请号：DE10232962

申请日：2002-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C11/408 ,  G11C11/4097 ,  G11C8/14 ,  G11C8/12 ,  G11C7/10

Abstract: A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.

公开(公告)号：DE10224180A1

公开(公告)日：2004-01-22

申请号：DE10224180

申请日：2002-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH ,  FISCHER HELMUT

IPC: H01L23/522 ,  H01L23/64 ,  H01L27/06 ,  H01L27/08 ,  H01L23/58

Abstract: An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.