公开(公告)号：DE10201179A1

公开(公告)日：2003-08-14

申请号：DE10201179

申请日：2002-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH ,  PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C7/10 ,  G11C11/407

Abstract: The circuit has at least two pairs of adjacent banks, a bundle of input/output lines, a controller and a changeover device. Only two bundles of read/write data lines are provided per pair of adjacent memory banks, the first associated with the first and second halves of the first and second banks and the second with the second and first halves of the first and second banks. The circuit has at least two pairs of adjacent banks (BK00-BK11), each with a number of memory cells in each bank, a bundle of input/output lines, a controller (120) and a changeover device (30) controllable depending on a clock signal for connecting the input/outputs lines to the first and second halves of the addressed memory bank during first and second half periods. Only two bundles (LDa,b) of read/write data lines are provided per pair of adjacent memory banks, the first associated with the first and second halves of the first and second banks and the second with the second and first halves of the first and second banks.

公开(公告)号：DE10341320B4

公开(公告)日：2007-05-10

申请号：DE10341320

申请日：2003-09-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH ,  GNAT MARCIN ,  VOLLRATH JOERG

IPC: H03F3/45 ,  G11C7/06 ,  H03G3/00

Abstract: A differential amplifier circuit has two input transistors, a load element, and a current source. A terminal for an input voltage is connected to a control terminal of a first input transistor. A terminal for a reference voltage is connected to a control terminal of a second input transistor. The two input transistors are connected in parallel between the load element and a terminal of the current source. A terminal for an internal reference potential is connected to a further terminal of the current source. A regulating circuit, is connected to the terminal for the voltage and to the terminal for the reference potential, and regulates the potential of the circuit dependent on changes in the reference voltage. Fluctuations of the reference voltage are compensated by regulation of the internal reference potential. As a result, the operating point of the circuit is stabilized independently of fluctuations of the reference voltage.

公开(公告)号：DE10119051A1

公开(公告)日：2002-10-31

申请号：DE10119051

申请日：2001-04-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEYNE PATRICK ,  MENCZIGAR ULLRICH

IPC: H03K5/1252 ,  G06F1/04

Abstract: A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The second signal path contains an RS flip-flop, upstream of which NAND gates are connected, which, for their part, are connected via different inverters to the input terminals for the clock signal and the enable signal, respectively.

公开(公告)号：DE102011118792A1

公开(公告)日：2012-07-12

申请号：DE102011118792

申请日：2011-11-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACKHAUSEN ULRICH ,  JEFREMOW MIHAIL ,  KERN THOMAS ,  MENCZIGAR ULLRICH

IPC: G11C7/06

Abstract: Einige erfindungsgemäße Ausführungsbeispiele betreffen einen Leseverstärker, der so konfiguriert ist, dass er die Steilheit einer Bitleitungs-Ladespannung bestimmt und die bestimmte Steilheit in Kombination mit einem Spannungspegel-Leseschema nutzt, um das Lesen von Daten aus einer der Bitleitung zugeordneten Speicherzelle zu unterstützen. Insbesondere ist eine Leseverstärkerschaltung so konfiguriert, dass sie eine Steilheit einer Bitleitungs-Ladespannung bestimmt und auf der Grundlage der bestimmten Steilheit die Steilheit der einem Leseverstärker bereitgestellten Bitleitungsspannung anpasst (zum Beispiel mittels Addierens eines dynamischen, steilheitsabhängigen Stroms zu einem Speicherzellenstrom, der so konfiguriert ist, dass er die Bitleitung lädt). Durch Anpassen der Steilheit der Bitleitungsspannung kann die Ladegeschwindigkeit von Speicherzellen, die sich in einem niederohmigen Zustand befinden (zum Beispiel mit einem hohen Zellenstrom und daher einem guten Signal/Rausch-Verhältnis) erhöht werden.

公开(公告)号：DE10241928A1

公开(公告)日：2004-03-18

申请号：DE10241928

申请日：2002-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH

IPC: G11C7/04 ,  G11C7/10 ,  G11C8/02 ,  G11C7/22 ,  G11C11/4076

Abstract: A synchronization unit for a semiconductor memory device (100), especially a high-frequency or DDR-RAM memory chip, which generates or receives an input clock signal (Cin), temperature adjusts it and outputs it (Cout) comprises a temperature-controlled delay device (10) producing a delay (20) to the clock signal which is then output. An Independent claim is also included for a semiconductor memory device comprising the above.

公开(公告)号：DE102011118792B4

公开(公告)日：2015-10-08

申请号：DE102011118792

申请日：2011-11-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACKHAUSEN ULRICH ,  JEFREMOW MIHAIL ,  KERN THOMAS ,  MENCZIGAR ULLRICH

IPC: G11C7/06 ,  G11C16/28

Abstract: Leseverstärkerschaltung, die Folgendes aufweist: eine Steilheitserkennungskomponente, die so konfiguriert ist, dass sie die Steilheit einer Bitleitungsspannung bestimmt und die Steilheit mittels eines Regelzyklus verbessert, um eine Ladegeschwindigkeit von Bitleitungen zu erhöhen, die Speicherzellen mit einem niederohmigen Zustand zugeordnet sind; und eine Pegelerkennungskomponente, die so konfiguriert ist, dass sie ein Leseverstärker-Ausgangssignal erzeugt, wenn die Bitleitungsspannung größer ist als ein Schwellenwert für den Spannungspegel; wobei das Verbessern der Steilheit der Bitleitungsspannung eine Zeit verringert, welche die Bitleitung benötigt, um den Schwellenwert für den Spannungspegel zu erreichen.

公开(公告)号：DE10119051B4

公开(公告)日：2006-12-28

申请号：DE10119051

申请日：2001-04-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEYNE PATRICK ,  MENCZIGAR ULLRICH

IPC: G06F1/04 ,  H03K5/1252

Abstract: A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The second signal path contains an RS flip-flop, upstream of which NAND gates are connected, which, for their part, are connected via different inverters to the input terminals for the clock signal and the enable signal, respectively.

公开(公告)号：DE10341320A1

公开(公告)日：2005-04-07

申请号：DE10341320

申请日：2003-09-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH ,  GNAT MARCIN ,  VOLLRATH JOERG

IPC: H03F3/45 ,  G11C7/06 ,  H03G3/00

Abstract: A differential amplifier circuit has two input transistors, a load element, and a current source. A terminal for an input voltage is connected to a control terminal of a first input transistor. A terminal for a reference voltage is connected to a control terminal of a second input transistor. The two input transistors are connected in parallel between the load element and a terminal of the current source. A terminal for an internal reference potential is connected to a further terminal of the current source. A regulating circuit, is connected to the terminal for the voltage and to the terminal for the reference potential, and regulates the potential of the circuit dependent on changes in the reference voltage. Fluctuations of the reference voltage are compensated by regulation of the internal reference potential. As a result, the operating point of the circuit is stabilized independently of fluctuations of the reference voltage.

公开(公告)号：DE10224180A1

公开(公告)日：2004-01-22

申请号：DE10224180

申请日：2002-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH ,  FISCHER HELMUT

IPC: H01L23/522 ,  H01L23/64 ,  H01L27/06 ,  H01L27/08 ,  H01L23/58

Abstract: An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.

公开(公告)号：DE10224180B4

公开(公告)日：2007-01-04

申请号：DE10224180

申请日：2002-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH ,  FISCHER HELMUT

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/58 ,  H01L23/64 ,  H01L27/06

Abstract: An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.