公开(公告)号：DE69822280D1

公开(公告)日：2004-04-15

申请号：DE69822280

申请日：1998-12-18

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SAi), at least one pair of master bitlines (MBLi, MBLi) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL1i, LBL1i, LBL2i, LBL2i), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch. The master bitlines may be arranged in either folded or open configurations. The master bitline pitch may be about twice the local bitline pitch.

公开(公告)号：DE10315049A1

公开(公告)日：2003-10-30

申请号：DE10315049

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C5/02

Abstract: The computer memory storage field (501) has first and second storage cell banks (510a,b) with zigzag edges (531,532). Blank or unused edges lie adjacent to each other. Each memory cell bank incorporates a memory block (330a,b). The system includes drivers (140a,b) for horizontal word lines (WL). Bit lines (BL) on the zigzag edges are arranged in pairs (BL-Paar) and cross each other (334) at intervals. The memory cells (331) consist of transistors.

公开(公告)号：DE10121182C1

公开(公告)日：2002-10-17

申请号：DE10121182

申请日：2001-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAMMERS STEFAN ,  GOGL DIETMAR ,  MUELLER GERHARD

IPC: G11C29/00 ,  G11C11/00

Abstract: The memory has a number of planes (1,2,3) having magnetoresistive memory cell fields combined in the form of a cross point array or transistor array, with redundant magnetoresistive memory cell fields (20) provided on the same chip and distributed above the individual planes of the memory matrix, or provided by one of the planes of the memory array, allowing defective memory cells in one plane to be replaced by redundant memory cells of a different plane.

公开(公告)号：DE10058047A1

公开(公告)日：2002-06-13

申请号：DE10058047

申请日：2000-11-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  SCHLOESSER TILL

IPC: H01L27/105 ,  G11C5/00 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/112 ,  G11C11/14

Abstract: An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive effect with a transistor control and cost-effective memory cells with a magnetoresistive effect with memory elements connected between the word lines and bit lines. The memory elements connected directly between the bit line and the word line are preferably inserted in memory cell arrays that can be stacked one above the other above the memory cells with the transistor, and thereby achieve a high integration density. The fact that the memory, which contains both types and thereby satisfies all the system requirements, is fabricated in one module and in one process sequence considerably lowers the fabrication costs.