公开(公告)号：JP2002093146A

公开(公告)日：2002-03-29

申请号：JP2001201320

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM assembly permitting to reduce an area necessary for line drive circuits by their effective arrangement and permitting space- saving design. SOLUTION: Word line drive circuits (6, 7) are assigned to two memory cell arrays (1, 2 or 2, 3) via each connecting node (4, 5) so that the drive circuit area is substantially reduced by half.

公开(公告)号：JP2002124080A

公开(公告)日：2002-04-26

申请号：JP2001235533

申请日：2001-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/06 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a device performing write-in in which loss of MRAM is less and in which memory cells having large resistance, short word lines and/or bit lines are not utilized. SOLUTION: This device has many memory cells (Z0, Z1, etc.), and these memory cells are provided respectively in a memory cell field between a word line(WL) and bit lines (BL, BL0, BL1, etc.). At the time of write-in process for the prescribed memory cell, voltage drop (V1-V2) is caused in the selected word line(WL) connected to this memory cell. When voltage V1 or voltage V2

公开(公告)号：JP2002203388A

公开(公告)日：2002-07-19

申请号：JP2001331484

申请日：2001-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  LAMMERS STEFAN ,  GOGL DIETMAR ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for obstructing undesirable programming in a MRAM device so that disablement of programming owing to scattered magnetic field of a memory cell being adjacent to a selection memory cell can be surely and simply obstructed. SOLUTION: A current IBL2 flowing in a bit line BL2 generates a scattered magnetic field in a MTJ memory cell I3 in an intersection part of a bit line BL3 and a word line WL1. Then an adequate compensation current IBL3 is made to flow in the bit line BL3 to suppress influence of this scattered magnetic field, scattered magnetic field in the MTJ memory cell I3 can be canceled by compensation magnetic field generated by this compensation current IBL3.

公开(公告)号：JP2002164515A

公开(公告)日：2002-06-07

申请号：JP2001275812

申请日：2001-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM module structure wherein high packing density of memory cell sections is achieved. SOLUTION: This MRAM module structure is constituted of a plurality of memory cell sections (A, P). The respective memory cell sections (A, P) are constituted of memory arrays (A) having a plurality of memory cells (WML, TL, HML) and peripheral circuits (P) surrounding edges of the memory arrays (A). The peripheral circuits (P) surround the memory arrays (A) in such a manner that the respective memory cell sections (A, P) have a cross structure in a plane, essentially. The memory cell sections (A, P) are so nested in each other that the memory cell sections (A, P) are offset mutually on individual rows (1, 2, 3).

公开(公告)号：JP2001273791A

公开(公告)日：2001-10-05

申请号：JP2001029947

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor memory constituted so that a redundant memory cell unit can be tested and the circuit configuration therefor is scarcely complexed inevitably. SOLUTION: This memory is provided with a memory cell MC arranged as a normal unit WL being addressable, a memory cell MC arranged as at least one unit RWL1 to replace the normal unit, an address bus 3 to which an address ADR can be applied, a redundant circuit 1 for selecting a redundant unit RWL1 connected to this address bus 3, and a processing unit 2. The processing unit 2 is connected to a terminal A of the address bus 3 at an input side, and connected to an input side of the redundant circuit 1 at an output side. The redundant unit RWL1 can be tested before programming of restoration information in the redundant circuit 1, moreover, the circuit is not made complex so much.

公开(公告)号：WO2005004162A3

公开(公告)日：2005-03-31

申请号：PCT/EP2004006190

申请日：2004-06-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

Inventor： DEBROSSE JOHN ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C11/16

CPC classification number: G11C11/15

Abstract: A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.

Abstract translation: 一种将信息存储在交叉点磁存储器阵列和交叉点磁存储器装置结构中的方法。 在写入操作期间磁隧道结（MTJ）上的电压降被最小化以防止损坏阵列的MTJ。 在写入操作期间，选定的MTJ，未选定的MTJ或两者上的电压降最小化，减小MTJ上的应力，降低泄漏电流，降低功耗并增加写入裕度。

公开(公告)号：WO0239454A3

公开(公告)日：2002-12-19

申请号：PCT/EP0112622

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG ,  FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

Inventor： FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/15

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/16

Abstract: The form of the supply lines in a cell field made from a matrix of columned and lined supply lines of a plurality of magnetic memory cells is optimised by diverging from a quadratic cross-section of the supply lines so that the magnetic field component Bx of the writing currents arranged on the plane of the cell field is rapidly reduced at an increasing distance from the increasing point of intersection.

Abstract translation: 从列和行的矩阵一个建成的引线的形状导致的多个磁存储单元的单元阵列被偏离引线的方形横截面的优化，使得磁场分量从交叉点Bx的随着距离的增加躺在单元阵列平面中的写电流的足够快地 降低。

公开(公告)号：WO0167248A3

公开(公告)日：2001-12-20

申请号：PCT/EP0101939

申请日：2001-02-21

Applicant: INFINEON TECHNOLOGIES AG ,  BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

Inventor： BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

IPC: G11C29/04 ,  G11C29/24 ,  G11C29/46 ,  G06F11/20 ,  G11C29/00

CPC classification number: G11C29/24 ,  G11C29/46

Abstract: The invention relates to a digital memory circuit with a memory matrix (50), comprising M regular rows and N regular columns and, furthermore, P

Abstract translation: 本发明涉及一种具有存储器矩阵（50）中，M个常规的行和N包含常规列，并且还P

公开(公告)号：DE50113843D1

公开(公告)日：2008-05-29

申请号：DE50113843

申请日：2001-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/3185 ,  G11C29/04 ,  G11C29/24

Abstract: An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

公开(公告)号：DE59914414D1

公开(公告)日：2007-08-30

申请号：DE59914414

申请日：1999-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAMMERS STEFAN ,  WEBER WERNER

IPC: G11C29/00 ,  G11C29/44

Abstract: The memory has a self test device, which is monolithically integrated with at least one memory field (1), and which has error counters (31) for word lines (WL) and column selection lines (CSL), a redundancy counter (32), nesting stores (41,42) for word lines and column selection lines to be repaired, comparators (21,22) and control unit. A comparator is connected to the nesting stores and comparators are connected to the error counter for the word lines and column selection lines. An Independent claim is included for a method to test the memory using a self-test device.