公开(公告)号：EP1062576A4

公开(公告)日：2003-08-27

申请号：EP99909696

申请日：1999-02-26

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  LEE YONG-FONG

IPC: G06F9/38 ,  G06F9/45

CPC classification number: G06F8/433 ,  G06F8/443 ,  G06F8/445 ,  G06F9/383 ,  G06F9/3842

Abstract: In one implementation of the invention, a computer implemented method used in compiling a program includes identifying a covering load, which may be one of a set of covering loads, and a redundant load. The covering load and the redundant load have a first and second load type, respectively. The first and the second load type each may be one of a group of load types including a regular load and at least one speculative-type load. In one implementation, the group of load types includes at least one check-type load. One implementation of the invention is in a machine readable medium.

公开(公告)号：EP3238091A4

公开(公告)日：2018-07-25

申请号：EP15873914

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： WANG CHENG ,  HARTONO ALBERT ,  BAGHSORKHI SARA S ,  WU YOUFENG

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3834 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3838

Abstract: In one embodiment vector conflict detection instructions are disclosed to perform dynamic memory conflict detection within a vectorized iterative scalar operation. The instructions may be performed by a vector processor to generate a partition vector identifying groups of conflict free iterations. The partition vector may be used to generate a write mask for subsequent vector operations.

公开(公告)号：EP3123321A4

公开(公告)日：2017-11-29

申请号：EP15769041

申请日：2015-03-23

Applicant: INTEL CORP

Inventor： GOTTSCHLICH JUSTIN E ,  POKAM GILLES A ,  HU SHILIANG ,  KASSA ROLF ,  WU YOUFENG ,  CALCIU IRINA

IPC: G06F9/455 ,  G06F11/36

CPC classification number: G06F9/467 ,  G06F11/34 ,  G06F11/362 ,  G06F11/3648

Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.

公开(公告)号：EP2997462A4

公开(公告)日：2017-01-18

申请号：EP13885815

申请日：2013-05-30

Applicant: INTEL CORP

Inventor： PARK HYUNCHUL ,  RONG HONGBO ,  WU YOUFENG

IPC: G06F9/38 ,  G06F9/45 ,  G06F9/46

CPC classification number: G06F8/4452 ,  G06F8/441 ,  G06F8/443 ,  G06F8/4451 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863

Abstract: In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.

公开(公告)号：EP2761433A4

公开(公告)日：2015-04-01

申请号：EP11872952

申请日：2011-09-27

Applicant: INTEL CORP

Inventor： WANG CHENG ,  WU YOUFENG

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/45 ,  G06F9/455

CPC classification number: G06F9/30098 ,  G06F8/434 ,  G06F8/4441 ,  G06F9/3834 ,  G06F9/45516

公开(公告)号：EP2684127A4

公开(公告)日：2014-11-26

申请号：EP11860992

申请日：2011-12-28

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG

IPC: G06F9/48 ,  G06F9/44 ,  G06F15/80

CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：EP2612248A4

公开(公告)日：2014-02-19

申请号：EP11822299

申请日：2011-08-03

Applicant: INTEL CORP

Inventor： HU SHILIANG ,  WU YOUFENG

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/14

CPC classification number: G06F12/0862 ,  G06F2212/1041 ,  G06F2212/502 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.