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公开(公告)号：MX2015002226A
公开(公告)日：2015-08-19
申请号：MX2015002226
申请日：2015-02-19
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO , LEE JAE-YOUNG
Abstract: En la presente descripción se describe un entrelazador de bits, un dispositivo de modulación codificada de bits entrelazados (BICM) y un método de entrelazado de bits; el entrelazador de bits incluye una primera memoria, un procesador y una segunda memoria; la primera memoria almacena una palabra código de revisión de paridad de baja densidad (LDPC) que tiene una longitud de 64800 y un índice de código de 5/15; el procesador genera una palabra código entrelazada al entrelazar la palabra código de LDPC con un criterio de grupo de bits; el tamaño del grupo de bits corresponde a un factor paralelo de la palabra código de LDPC; la segunda memoria proporciona la palabra código entrelazada a un modulador para mapeo de 64 símbolos.
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公开(公告)号：CA2880594A1
公开(公告)日：2015-07-29
申请号：CA2880594
申请日：2015-01-28
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KWON SUN-HYOUNG , LEE JAE-YOUNG , KIM HEUNG-MOOK , HUR NAM-HO
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：CA2564044C
公开(公告)日：2013-08-06
申请号：CA2564044
申请日：2005-05-12
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： EUM HO-MIN , LEE YONG-TAE , KIM SEUNG-WON , KIM HEUNG-MOOK , SEO JAE-HYUN , PARK SUNG-IK , LEE SOO-IN
Abstract: Provided is a frequency synchronizing apparatus and method that can synchronize frequencies between receiving signals and transmitting signals by extracting a carrier error and sampling timing error information in a synchronization process of the receiving signal from a main transmitter or another repeater and reflecting them in the transmitting signal in an on-channel repeater. The apparatus includes a carrier recovery means for compensating a carrier frequency error of a receiving signal; a timing recovery means for compensating a sampling timing error of the receiving signal; a carrier error reflecting means for reflecting the carrier frequency error extracted from the carrier recovery means to a transmitting signal; and a timing error reflecting means for reflecting the sampling timing error extracted from the timing recovery means to the transmitting signal. The present invention is used to form an on-channel repeating network in any transmission system including a digital television broadcasting system.
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公开(公告)号：CA2698669A1
公开(公告)日：2009-03-12
申请号：CA2698669
申请日：2008-05-15
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： LEE JAE-YOUNG , PARK SUNG-IK , EUM HO-MIN , SEO JAE-HYUN , KIM HEUNG-MOOK , LIM JONG-SOO , LEE SOO-IN
IPC: H04B7/14
Abstract: Provided is an identification signal analyzing apparatus and method for compensating power of a channel profile occurring at a conventional identification signal analyzing apparatus by using a power compensation. The identification signal analyzing apparatus includes: an identification signal generator for generating an identification signal identical to a known identification signal inserted by a transmission device; a partial correlator for calculating a correlation value between a received signal including the known identification signal inserted by the transmission device and the identification signal generated by the identification signal generator through a partial correlation; a power compensator for compensating power of the correlation value calculated by the partial correlator; and a channel profile extractor for extracting a channel profile from the correlation value compensated by the power compensator.
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公开(公告)号：CA2605834A1
公开(公告)日：2006-11-02
申请号：CA2605834
申请日：2005-12-29
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KIM HEUNG-MOOK , SEO JAE-HYUN , KIM SEUNG-WON , LEE SOO-IN , EUM HO-MIN , PARK SUNG-IK , LEE YONG-TAE
IPC: H04B7/14
Abstract: Provided are an on-channel repeater and a method thereof. The on-channel repeater can extract reception channel information from signals transmitted from a main transmitter or another repeater, compensate for channel distortion caused on a transmission channel by inversely reflecting the extracted reception channel information to the received signals, and transmit the channel-distortion compensated signals through the same channel as a reception channel, and a method thereof. The on-channel repeater includes: a receiver for receiving RF signals transmitted from outside; a down-converter for down-converting the received RF signals into signals of a desired band; a channel-estimator for estimating an inverse value of a reception channel based on the down-converted signals; an adaptation filter for compensating for channel distortion by using a filter having the inverse value of the estimated reception channel; an up-converter for up-converting the channel distortion-compensated signals into RF signals; and a transmitter for transmitting the up-converted RF signals.
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Patent Agency Ranking
公开(公告)号：MX2014012116A
公开(公告)日：2016-02-15
申请号：MX2014012116
申请日：2014-10-07
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO
Abstract: Se describe un codificador de revisión de paridad de baja densidad (LDPC), un decodificador de LDPC y un método codificador de LDPC; el codificador de LDPC incluye una primera memoria, una segunda memoria y un procesador; la primera memoria almacena una palabra código de LDPC que tiene una longitud de 64800 y un índice de código de 2/15; la segunda memoria es inicializada a 0; el procesador genera la palabra código de LDPC que corresponde a los bits de información al realizar la acumulación con respecto a la segunda memoria al usar una secuencia que corresponde a una matriz de revisión de paridad (PCM).
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公开(公告)号：MX2014012115A
公开(公告)日：2016-02-15
申请号：MX2014012115
申请日：2014-10-07
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO
Abstract: Se describe un codificador de revisión de paridad de baja densidad (LDPC), un decodificador de LDPC y un método codificador de LDPC; el codificador de LDPC incluye una primera memoria, una segunda memoria y un procesador; la primera memoria almacena una palabra código de LDPC que tiene una longitud de 16200 y un índice de código de 5/15; la segunda memoria es inicializada a 0; el procesador genera la palabra código de LDPC que corresponde a los bits de información al realizar la acumulación con respecto a la segunda memoria al usar una secuencia que corresponde a una matriz de revisión de paridad (PCM).
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公开(公告)号：CA2864647A1
公开(公告)日：2016-02-14
申请号：CA2864647
申请日：2014-09-25
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：CA2864635A1
公开(公告)日：2016-02-14
申请号：CA2864635
申请日：2014-09-25
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：CA2864630A1
公开(公告)日：2016-02-14
申请号：CA2864630
申请日：2014-09-25
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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