公开(公告)号：JP2002009179A

公开(公告)日：2002-01-11

申请号：JP2000186763

申请日：2000-06-21

Applicant: SONY CORP

Inventor： NOMOTO KAZUMASA ,  AOZASA HIROSHI ,  FUJIWARA ICHIRO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enhance charge injection efficiency by improving retention characteristics and charge retention characteristics. SOLUTION: A non-volatile semiconductor storage device has a semiconductor layer supported on a semiconductor board or a board, an insulation layer formed on the surface area CH and including in the inside a charge accumulation layer FG in which charge is injected from a board side, and a control electrode on the insulation film. It has a bottom insulation film BTM including an area different in nitrogen concentration in the film thickness direction between the semiconductor surface area CH of the board side and the charge accumulation layer FG. The nitrogen concentration distribution in the film thickness direction has the maximum value, and the peak is unevenly distributed on the board side from the film thickness center of the bottom insulation film BTM. Furthermore, nitrogen concentration is low in the neighborhood of an interface with the semiconductor surface area CH, and increases toward the inside of the bottom insulation film. The nitrogen concentration distribution of the bottom insulation film BTM exposes the semiconductor surface area CH to plasma containing nitrogen atoms, and is obtained by nitriding.

公开(公告)号：JP2001230332A

公开(公告)日：2001-08-24

申请号：JP2000269892

申请日：2000-09-01

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: B82B1/00 ,  G11C16/04 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To improve the injection efficiency and locally inject charges in a part of distributed regions of charge storing means to store a plurality of bits in an MONOS type memory transistor. SOLUTION: The memory comprises first conductivity type channel forming regions, second conductivity type source-drain regions (bit line BLi, BLi+1), gate insulation films 10a, 10b (or 10), 17 on the channel forming regions, gate electrodes 15a, 15b (or 18), CG, and charge storing means (charge traps) which are discretized in a plane facing the channel forming regions and in a film thickness direction and formed in the gate insulation films so that, in operation, hot electrons due to e.g. an inter-band tunnel current are injected from the source-drain regions. In the gate insulation film, a third region 17 (R3) having no charge storing means exists between a first memory area 10a (R1) and a second memory area 10b (R2) into which the hot electrons are injected locally.

公开(公告)号：JP2001168219A

公开(公告)日：2001-06-22

申请号：JP36187799

申请日：1999-12-20

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: H01L21/8247 ,  B82B1/00 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enhance a write speed, keeping an operation voltage low, in a MONOS-type memory transistor. SOLUTION: This device is equipped with a substrate 1, a channel formation region 1a for a semiconductor provided at the surface of the substrate, first and second impurity regions 2 and 4 made at the surface of the substrate with the channel formation region 1a in-between, a gate insulating film 6 including within a charge accumulating means (carrier trap) dispersed in the direction of interior of the face opposed to the channel formation area 1a and the direction of film thickness, and a gate electrode 8 provided on the gate insulating film 6. Charge is accelerated in the vertical direction to the substrate such as substrate hot electron, secondary collision ionized hot electron, or the like, or a step 1b is made at the surface of the channel formation region 1a. As a result, the charge accumulating means comes to be positioned in the direction of charge accumulation, and implantation efficiency rises.

公开(公告)号：JP2001085546A

公开(公告)日：2001-03-30

申请号：JP26450199

申请日：1999-09-17

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: G11C16/02 ,  B82B1/00 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enhance convergence of an erasure Vth (threshold voltage) of anMONOS(metal oxide nitride oxide semiconductor) transistor, and to accurate the erasing speed. SOLUTION: This erasing method performs writing and erasure and then writing and erasure at least once or several times, after the erasure as operation for erasure which can improves the convergence of an erasure Vth of a memory transistor, including charge storage means which are made discrete in plane in a gate insulating film interposed of a channel formation region and a gate electrode of a semiconductor. To accurate erasing speed, an erasing voltage and/or an erasure time is optimized and set for the phenomenon where the absolute value of a voltage at an inflection point having an extremum on the erasure side increases as the voltage application time is shortend on the hysteresis curve of threshold voltage variation with the applied voltage of the memory transistor.

公开(公告)号：JP2001024075A

公开(公告)日：2001-01-26

申请号：JP19870499

申请日：1999-07-13

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: G11C16/02 ,  B82B1/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a memory transistor having a charge storage means such as FG, MONOS, etc., which can be suitably scaled to a gate length of 0.13 μm or less. SOLUTION: The memory includes a source region 2, a drain region 4, a gate insulating film 6 provided on a channel formation region 1a and having a charge storage means (charge trap) therein, and a gate electrode 8 provided thereon. An impurity concentration profile of the channel formation region 1a, source region 2 and/or drain region 4 is set to be varied to gradually increase a junction breakdown voltage of the source region 2 and/or drain region 4 from an impurity concentration profile optimum for suppressing a threshold reduction caused when a gate length is shortened to a predetermined rate (e.g. 10% or less). For example, when the profile is set so that the threshold is reduced by 15% or more, a short channel effect can be inhibited. As a result, even when the channel impurity concentration is relatively high, a write inhibit voltage can be applied.

公开(公告)号：JP2000031435A

公开(公告)日：2000-01-28

申请号：JP19307798

申请日：1998-07-08

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: G11C16/04 ,  B82B1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To improve a read disturb characteristics in an NAND type nonvolatile memory, wherein a charge storage means is discretized in plane within a memory transistor. SOLUTION: Memory transistors M11, etc., comprise charge storage means which are, in a gate insulating film between a substrate surface and a gate electrode, discretized in the plane facing a channel formation region. Bypass transistors B11, connected in parallel to a memory transistor in each memory cell, common line BPL, etc., for common connection with the plurality of gate electrodes, a common line control means 22 which controls a bypass transistor with a voltage applied to the common line, are provided. The common line may be shared with a word line. The common line control means 22 applies a voltage at reading a data, to the common line, which is higher than the gate application voltage of a selection memory transistor and lower than a threshold voltage Vth (W) in its writing state, so that a bypass transistor in a non- selection cell in a selection NAND array is conductive.

公开(公告)号：JPH11330277A

公开(公告)日：1999-11-30

申请号：JP27218498

申请日：1998-09-25

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: G11C16/02 ,  B82B1/00 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To improve the read disturb property of a nonvolatile memory having a micro gate length and realize one transistor cell. SOLUTION: A plurality of memory transistors, having comparatively thickened tunnel insulation films are arranged like a matrix, constituting a memory array, and in the source and/or drain of a nonselective row memory transistors M21 arranged in a row not including a selective memory transistor M11 , a nonselective row vias voltage between source potential and gate potential during reading of selective transistor M11 is applied to the channel formation area in the reverse vias direction for example, and further a voltage between a voltage to be applied during reading of selective memory transistor M11 to the gate and grounding voltage is applied to the source of the selective memory transistor M11 . Then a voltage equivalent to or lower than that to the source of the selective memory transistor M11 is applied to the gate of the non-selective line.

公开(公告)号：JPH11224940A

公开(公告)日：1999-08-17

申请号：JP12146198

申请日：1998-04-30

Applicant: SONY CORP

Inventor： AOZASA HIROSHI ,  HAYASHI YUTAKA ,  FUJIWARA ICHIRO

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To effectively prevent erroneous writing into non-selected cells which accompanies reduction in programming voltage. SOLUTION: A nonvolatile semiconductor memory device has memory cells M11a to M1na, which perform basic information storing operations by injecting or drawing charges into or from charge storage means by applying a voltage to first control electrodes (e.g. word liens WL11 to WL1n) deposited on channel- forming regions of a semiconductor via an insulating film including the charge storage means, and cells (e.g. other memory cells or selected cells) for transmitting a predetermined potential to the channel-forming regions of the memory cells in injecting or drawing the charges. Second control electrodes 22, which are capacitively coupled to semiconductor regions between the memory cells and the cells for transmitting the predetermined potential and control the potential and the formation of inter-cell channels or depletion layer in the semiconductor regions, are formed in impurity regions between cells via an insulating film 20.

公开(公告)号：JPH10334525A

公开(公告)日：1998-12-18

申请号：JP21685297

申请日：1997-08-11

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: G01B21/30 ,  G01N37/00 ,  G01Q20/02 ,  G01Q20/04 ,  G01Q60/24 ,  G01Q60/30 ,  G01Q60/46 ,  G01Q70/06 ,  G01Q80/00 ,  G11B9/00 ,  G11B9/02 ,  G11B9/14

Abstract: PROBLEM TO BE SOLVED: To enable high-density recording and reproducing and to improve recording and reproducing speeds by arraying plural pieces of needle-like electrodes, recording information in parallel with the plural recording bits of the prescribed region of a corresponding recording medium or reproducing the plural recording bits by the needle-like electrodes arrayed in plural pieces. SOLUTION: The recording medium 10 is formed of an electrode layer on a substrate and a charge accumulation material film of SiN or the like which is a hetero layer or dielectric hetero layer thereon. On the other hand, a recording head HP is constituted by integrating plural pieces of conductive cantilevers 22 having the needle-like electrodes 21 at the front ends in parallel. In the case of recording, prescribed recording pulse are impressed on the cantilevers 22 to record information on the recording medium 10 by locally implanting or releasing electrons to or from the carrier traps existing near the SiN film. In the case of reproduction, the recorded information is reproduced by subjecting the local surface potential of the recording medium 10 to the detection of the static capacity changes between the charge implanted regions and non-implanted regions by operating plural pieces of the needle-like electrodes 21 in parallel.

公开(公告)号：JPH05158089A

公开(公告)日：1993-06-25

申请号：JP31934491

申请日：1991-12-03

Applicant: SONY CORP

Inventor： BOON HAWAASU ,  FUJIWARA ICHIRO ,  ASAI NOBUTOSHI ,  KISHII NORIYUKI ,  TAMURA SHINICHIRO

IPC: C09K9/02 ,  G02F1/35 ,  G02F1/355 ,  G02F1/361

Abstract: PURPOSE:To stably transfer a monomolecular film on a substrate as a film and to stably form a Langmuir-Blodgett(LB) film by using an org. thin film in which monomolecular layers contg. a specified compd. are laminated in plural layers. CONSTITUTION:This org. nonlinear optical material is shown by the formula where 20