公开(公告)号：EP2893618B1

公开(公告)日：2016-07-06

申请号：EP13745121.7

申请日：2013-08-06

Applicant: Robert Bosch GmbH

Inventor： STIEFEL, Tobias

IPC: H02K11/00

CPC classification number: H05K1/0259 ,  H02K11/26 ,  H05K2201/10204

公开(公告)号：EP2241168A4

公开(公告)日：2012-09-12

申请号：EP09702108

申请日：2009-01-08

Applicant: ROSEMOUNT INC

Inventor： ERICKSEN CHRISTOPHER LEE ,  GOLDBERG HOWARD DAVID ,  MEYER JOHN CHARLES

IPC: H05K1/14 ,  H05K5/00 ,  H05K7/14

CPC classification number: H05K1/147 ,  H05K1/0256 ,  H05K2201/10204 ,  H05K2201/2036 ,  Y10T29/49826

公开(公告)号：EP2283717A1

公开(公告)日：2011-02-16

申请号：EP09757212.7

申请日：2009-05-28

Applicant: SARTORIUS AG

Inventor： WEITEMEIER, Swen ,  OLDENDORF, Christian

IPC: H05K1/02

CPC classification number: G01R31/2815 ,  G01R31/2839 ,  G06F21/86 ,  H05K1/0275 ,  H05K2201/10151 ,  H05K2201/10204

Abstract: The invention relates to an electronic device comprising a circuit board (10), with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM) and a controller. The invention is characterised in that the controller carries out a real-time test of the circuit board by means of a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive source-specific, or individual circuit board network with at least one element with a capacitive action, wherein the capacitive element is a conductor surface (221) forming a capacitor in the assembled state with a corresponding conductor surface (222' '), on the device, connected to the electrical circuit (18) by means of a contact element in the assembled state, such that the capacitive value of the element with a capacitive action in the assembled state is different from the capacitive value thereof in the disassembled state.

Abstract translation: 本发明涉及一种包括电路板（10）的电子设备，具有一组输入触点（IN / COM），一组输出触点（OUT / COM）和连接在输入触点之间的电路（18） IN / COM）和输出触点（OUT / COM）和一个控制器。 本发明的特征在于，控制器通过引入到电路中的测试信号来对电路板进行实时测试，电路（18）被设计为被动的源特定或单独的电路板 网络，其具有至少一个具有电容作用的元件，其中所述电容元件是形成电容器的导体表面（221），所述导体表面（221）在组装状态下具有相应的导体表面（222“），所述导体表面（222”）连接到所述电路 在装配好的状态下，具有电容作用的元件的电容值不同于其在分解状态下的电容值。

公开(公告)号：EP2019574A3

公开(公告)日：2009-07-08

申请号：EP08013360.6

申请日：2008-07-24

Applicant: TDK Corporation

Inventor： Kanemaru, Yoshikazu ,  Ohkawa, Hiroshige ,  Kawabata, Kenichi

IPC: H05K3/28

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3511 ,  H05K3/0052 ,  H05K3/4644 ,  H05K2201/10204 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of manufacturing an electronic component-embedded board is provided which is capable of suppressing warpage without requiring complicated processes at low cost and which offers high productivity and economic efficiency. A worksheet 100 includes insulating layers 21 and 31 on one surface of an approximately rectangular substrate 11, and electronic components 41 and chip-like dummy parts 51 primarily made from the same material as the primary material of the electronic component 41 are embedded into the insulating layer 21. Chip-like dummy parts 51 are disposed in an unmounted portion of the electronic components 41 in, for example, a frame-like arrangement so as to surround the plurality of electronic components (groups) 41.

Abstract translation: 提供一种制造电子部件嵌入式板的方法，其能够在不需要以低成本进行复杂的工艺的情况下抑制翘曲并且提供高生产率和经济效率。 工作片100在近似矩形的基板11的一个表面上包括绝缘层21和31，并且主要由与电子部件41的主要材料相同的材料制成的电子部件41和芯片状的虚拟部分51嵌入绝缘层 芯片状的虚拟部件51以例如框状的方式设置在电子部件41的未安装部分中，以围绕多个电子部件（组）41。

公开(公告)号：EP1320288B1

公开(公告)日：2009-04-15

申请号：EP02255035.4

申请日：2002-07-17

Applicant: FUJITSU LIMITED

Inventor： Kikuchi, Shunichi, c/o Fujitsu Limited ,  Yamada, Mitsutaka, c/o Fujitsu Limited ,  Iketaki, Kenji, c/o Fujitsu Limited

IPC: H05K3/34 ,  H05K1/02

CPC classification number: H05K1/0209 ,  H05K1/0201 ,  H05K3/3494 ,  H05K2201/066 ,  H05K2201/09781 ,  H05K2201/10204 ,  H05K2203/1121 ,  H05K2203/304 ,  Y10T29/4913 ,  Y10T29/49144

公开(公告)号：EP1566995A1

公开(公告)日：2005-08-24

申请号：EP04003951.3

申请日：2004-02-20

Applicant: Research In Motion Limited

Inventor： Connell, David James ,  Christian, Beverley Howard

IPC: H05K13/08 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K1/111 ,  G01N2013/0225 ,  H05K1/0269 ,  H05K3/341 ,  H05K3/3436 ,  H05K13/046 ,  H05K13/08 ,  H05K2201/094 ,  H05K2201/09781 ,  H05K2201/10204 ,  Y02P70/611

Abstract: This invention provides an evaluation board (10) for evaluating one or more aspects of a surface mount technology system. In one aspect, the evaluation board has a substrate with at least one surface (12). A plurality of board pad patterns (14), each including a plurality of board pads (16), is formed on the surface. The different board pad pattern may have different shaped, sized and spaced board pads, allowing the characteristics of a surface mount technology to be tested on some or all of the board pad patterns at the same time and under uniform conditions. In another aspect, the surface may have a plurality of area-filled board pads similarly allowing a surface mount technology to be tested on the various area-filled board pads.

Abstract translation: 本发明提供一种用于评估表面贴装技术系统的一个或多个方面的评估板（10）。 一方面，评估板具有至少一个表面（12）的基底。 在表面上形成有多个板焊盘图案（14），每个板焊盘图案包括多个板焊盘（16）。 不同的板焊盘图案可以具有不同的形状，尺寸和间隔的板焊盘，允许表面贴装技术的特性在同一时间和均匀条件下在一些或所有板焊盘图案上进行测试。 在另一方面，表面可以具有多个区域填充的板焊盘，其类似地允许在各种填充面板的板焊盘上测试表面贴装技术。

公开(公告)号：EP1182919A3

公开(公告)日：2003-05-21

申请号：EP01119985.8

申请日：2001-08-18

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Uchiyama, Hiroshi ,  Hachimura, Tetsutarou ,  Okuda, Osamu ,  Yoshida, noriaki

IPC: H05K13/08

CPC classification number: H05K3/0008 ,  H05K1/0269 ,  H05K3/303 ,  H05K13/08 ,  H05K2201/09918 ,  H05K2201/10204

Abstract: An offset measuring board is formed of a rectangular metal plate which can be positioned to a component mounting position by a positioning device and which has at least in proximity to one corner portion thereof a recognition through hole, as a recognition mark, having a black bottom face within a recessed portion.

公开(公告)号：EP0264243A3

公开(公告)日：1989-01-25

申请号：EP87308979.1

申请日：1987-10-09

Applicant: LOMA PARK ASSOCIATES INC.

Inventor： Wilent, John W. ,  Benson, Robert F. ,  Sparks, Robert A.

IPC: H05K13/00 ,  G03F9/00

CPC classification number: H05K3/4638 ,  H05K3/0008 ,  H05K3/0047 ,  H05K3/4611 ,  H05K2201/09918 ,  H05K2201/10204 ,  Y10T83/178 ,  Y10T408/03 ,  Y10T408/08 ,  Y10T408/21

Abstract: A method and apparatus for optimizing the drilling position of a multi-layer printed circuit board prior to drilling. A template (115) having precisely located target holes (A',B',C',D') and fixture reference marks (118, 119) provides initial coordinate reference information for multi-layer printed circuit boards (25) to be inspected by x radiation. Each board (25) is processed by insertion into a holding fixture, examination of four quadrant target areas using x-ray sources (21-24) and detectors (26-29), digitization of the target area images in each quadrant, and computation of the optimum board position in a follow-on drilling apparatus. After optimization, three reference holes are punched along one edge of the board (25) to provide accurate fiducial positioning marks when the board is placed in the drilling apparatus.

公开(公告)号：EP0264243A2

公开(公告)日：1988-04-20

申请号：EP87308979.1

申请日：1987-10-09

Applicant: LOMA PARK ASSOCIATES INC.

Inventor： Wilent, John W. ,  Benson, Robert F. ,  Sparks, Robert A.

IPC: H05K13/00 ,  G03F9/00

CPC classification number: H05K3/4638 ,  H05K3/0008 ,  H05K3/0047 ,  H05K3/4611 ,  H05K2201/09918 ,  H05K2201/10204 ,  Y10T83/178 ,  Y10T408/03 ,  Y10T408/08 ,  Y10T408/21

Abstract: A method and apparatus for optimizing the drilling position of a multi-layer printed circuit board prior to drilling.
A template (115) having precisely located target holes (A',B',C',D') and fixture reference marks (118, 119) provides initial coordinate reference information for multi-layer printed circuit boards (25) to be inspected by x radiation. Each board (25) is processed by insertion into a holding fixture, examination of four quadrant target areas using x-ray sources (21-24) and detectors (26-29), digitization of the target area images in each quadrant, and computation of the optimum board position in a follow-on drilling apparatus. After optimization, three reference holes are punched along one edge of the board (25) to provide accurate fiducial positioning marks when the board is placed in the drilling apparatus.

Abstract translation: 一种用于在钻孔之前优化多层印刷电路板的钻孔位置的方法和装置。 具有精确定位的目标孔（A'，B'，C'，D'）和夹具参考标记（118,119）的模板（115）为要检查的多层印刷电路板（25）提供初始坐标参考信息 通过x辐射。 每个板（25）通过插入保持夹具中进行处理，使用x射线源（21-24）和检测器（26-29）检查四个象限目标区域，每个象限中的目标区域图像的数字化，以及计算 在后续钻井设备中的最佳板位置。 优化后，当板放置在钻孔装置中时，沿着板（25）的一个边缘冲压三个参考孔，以提供准确的基准定位标记。

公开(公告)号：WO2016150912A1

公开(公告)日：2016-09-29

申请号：PCT/EP2016/056146

申请日：2016-03-21

Applicant: SIVANTOS PTE. LTD. ,  BEYFUSS, Stefanie ,  KRAL, Holger ,  FREELS, Björn ,  KUHN, Johannes

Inventor： BEYFUSS, Stefanie ,  KRAL, Holger ,  FREELS, Björn ,  KUHN, Johannes

IPC: H05K3/28 ,  H01R25/00

CPC classification number: H05K3/341 ,  H04R25/00 ,  H04R25/60 ,  H05K3/0076 ,  H05K3/284 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10204 ,  H05K2201/1028 ,  H05K2203/0228 ,  H05K2203/0557 ,  H05K2203/107

Abstract: Die Erfindung betrifft ein Verfahren (2) zur Herstellung einer Schaltung (4), insbesondere einer Hörhilfe (6), bei dem eine Leiterplatte (10) mit einem ersten Bereich (14) und mit einem zweiten Bereich (12), die mittels einer Grenze (18) getrennt sind, bereitgestellt wird. An der Leiterplatte (10) wird ein Bauteil (24) angebracht, wobei das Bauteil (24) auf der Grenze (18) positioniert wird. Der erste Bereich (14) wird mittels einer eine Kante (42) aufweisenden Maske (38) abgedeckt, wobei die Kante (42) auf dem Bauteil (24) positioniert wird, und die Leiterplatte (10) wird mit einer Beschichtung (46) versehen. Die Beschichtung (46) wird im Bereich des Bauteils (24) aufgetrennt, und die Maske (38) wird entfernt.

Abstract translation: 本发明涉及一种方法，（2）用于制造电路（4），特别是助听器（6），其中一个电路板（10）通过的限制装置具有第一区域（14）和第二区域（12） （18）被分离，提供了一种。 一个部件（24）安装在印刷电路板（10），其中上边界（18）的部件（24）被定位。 所述第一区域（14）被覆盖有掩膜（38）的边缘（42）的装置，所述边缘（42）定位在所述部件（24）上，并且所述电路板（10）上设置有涂层（46） ， 所述涂层（46）在部件（24）和所述掩模（38）被去除的区域中分离出来。