-
公开(公告)号：JPH1083673A
公开(公告)日：1998-03-31
申请号：JP16164297
申请日：1997-06-18
Applicant: CIRRUS LOGIC INC
Inventor： TAYLOR RONALD T
IPC: G11C11/41 , G06F13/16 , G11C11/401
Abstract: PROBLEM TO BE SOLVED: To provide an improved I/O subsystem and an I/O subsystem device (especially core logic) which performs independent various tasks, and/or minimizes a disparity between devices operating with different speed one another on performance. SOLUTION: A memory 20 has a first memory cell array 100 and a second memory cell array 102. A first data port 118 enables transfer of data with the first array 100, a second data port 120 enables transfer of data with the second array 102. Also, a memory system 20 is provided with a circuit 122 which controls transfer of data with the first array 100 through the first data port 118 in some selected mode, and controls delivering data with the second array 102 through the second data port 120. Then, transfer of data with the first array 100 and the second array 102 is performed asynchronously.
-
公开(公告)号：JPH1063866A
公开(公告)日：1998-03-06
申请号：JP17233097
申请日：1997-06-27
Applicant: CIRRUS LOGIC INC
Inventor： LARSON MICHAEL KERRY , WILDE DANIEL P
Abstract: PROBLEM TO BE SOLVED: To make logic simple and enable fast interpolation by providing a polygon state machine which loads and selects initial values as to a 1st and a 2nd accumulator and a counter and increases the 1st and 2nd accumulators and counter. SOLUTION: The polygon state machine 350 asserts an LD signal and a MAIN signal and then starts polygon rendering operation. Multiplexers 315 and 365 select initial main values in response and they are loaded to the counter 320 and accumulators 340 and 360 together with the initial values. Then an increment signal is generated by the machine 350 and COUNT0 is counted down to zero. Each time an increment is given, an X value and a width value are generated by the accumulators 340 and 360 as to each scan line in the upper half of the polygon. When COUNT0 reaches zero, a COUNT1 value is inspected.
-
73.发明专利
公开(公告)号：JPH1055156A
公开(公告)日：1998-02-24
申请号：JP12113997
申请日：1997-05-12
Applicant: CIRRUS LOGIC INC
Inventor： SHARMA SUDHIR , RAO MOHAN G R , RUNAS MICHAEL E
Abstract: PROBLEM TO BE SOLVED: To provide a circuit, a system and a method for realizing a dual scanning display in which a wasteful memory space and related costs are reducable by reducing the overhead of frame buffer subsystems. SOLUTION: A display controller 104 to be used together with an operatable display device 107 is provided so as to display images on a screen. The display controller 104 is provided with circuits 201-210 generating an image on the first area of the screen by supplying first data to the display device 7. Here, the first data are taken out from an external frame buffer 108. Moreover, the display controller 104 is provided with circuits 205, 210 generating an image on the second area of the screen by supplying second data to the display device 107. Then, the second data are taken out from an internal frame buffer 206.
-
公开(公告)号：JPH1027138A
公开(公告)日：1998-01-27
申请号：JP5189097
申请日：1997-03-06
Applicant: CIRRUS LOGIC INC
Inventor： RAO G R MOHAN
Abstract: PROBLEM TO BE SOLVED: To substitute a normally operating row or column of another memory element for a defective row or column of one memory element by providing a crossbar switch which switches the address corresponding to a defective cell of a 1st memory to to a redundant cell in a 2nd memory. SOLUTION: Respective memory units 201 receive data, a clock, and a control signal from core logic 103. A programmable crossbar switch 202 makes it possible to convert the addresses corresponding to some position in a defective row or column of one memory unit 201 into redundant addresses ADDR1-ADDR0 and reallocate the new redundant addresses to another selected memory unit 201 including an unused redundant row or column in the redundant addresses. This system is so designed that when a proper choice is made, propagation delay generated newly by the programmable crossbar switch 202 is about 5 6 nanoseconds.
-
公开(公告)号：JPH1021557A
公开(公告)日：1998-01-23
申请号：JP7019397
申请日：1997-03-24
Applicant: CIRRUS LOGIC INC
Inventor： SUPINO LOUIS , ROMANO PAUL M , REIFF FRANCIS H
Abstract: PROBLEM TO BE SOLVED: To provide an optical disk drive servo control system having not so high sensitivity to a parameter change, capable of controlling transition better and reducing the execution cost of a complex adaptive linear controller. SOLUTION: The optical disk memory system is provided with a sliding mode controller 23 actuating an optical read head assembly on an optical disk 14 during focus capture, focus tracking, track seek and center line tracking. This sliding mode controller 23 operates while switching positive and negative feedback to follow a prescribed phase state locus by fitting a prescribed phase state (e.g. position error and speed of read head).
-
Patent Agency Ranking
公开(公告)号：JPH09244987A
公开(公告)日：1997-09-19
申请号：JP31238596
申请日：1996-11-22
Applicant: CIRRUS LOGIC INC
Inventor： SUTEIIBUN EI SUMISU , JIYAFUAA NAJI
Abstract: PROBLEM TO BE SOLVED: To enable plural PC card controllers to use the legacy software in an offered computer system by providing a specific socket, a specific means which recognizes the address designation, etc. SOLUTION: A notebook type computer 10 and a docking station 12 are prepared. Then each of PC card controllers 38, 58 and 60 which are connected to the 1st buses 24 and 52 has the sockets 40, 42, 62, 64 and 70 to which the devices can be connected, a socket point register, an index register, a means which updates the index register, and a means which recognizes the address designation of those sockets 40 to 70 respectively. The address designation recognition means includes a means which updates the data register pointed by the index register with the write data when the partial matching is secured between a part of the socket pointer information and that of the updated index.
-
公开(公告)号：JPH09244597A
公开(公告)日：1997-09-19
申请号：JP30527396
申请日：1996-11-15
Applicant: CIRRUS LOGIC INC
Inventor： AREKUSANDAA JIEI EGURITSUTO , ROBIN ESU HAN
Abstract: PROBLEM TO BE SOLVED: To reduce or eliminate a flicker in particular in gray scale by chang ing a phase of a shading duty cycle as to a subpixel of each color in using an offset value added to a frame counter. SOLUTION: An output from the frame counter 301 is given direct to a pattern LUT 304A. This output of the frame counter 301 is also given to adders 309 and 310 respectively, while these adders 309 and 310 receive offset values from registers 311 and 312 as the other outputs respectively. Upon addition of the offset values from the registers 311 and 312 through the adders 309 and 310, a pattern position, i.e., a phase is offset. With regard to the duty cycles of, for example, the blue and green subpixels, the duty cycle of the read subpixel is offset by one or two clock cycles respectively.
-
公开(公告)号：JPH09231506A
公开(公告)日：1997-09-05
申请号：JP12070796
申请日：1996-05-15
Applicant: CIRRUS LOGIC INC
Inventor： MAAKU ESU SUPAABETSUKU , RICHIYAADO TEII BEERENZU
Abstract: PROBLEM TO BE SOLVED: To prevent the generation of a cross talk phenomenon accompanied with a write VFO frequency by introducing an inter-polating type timing recovery loop into an amplitude read channel. SOLUTION: A frequency synthesizer 52 generates a sampling clock given to a sampling device 24 through a line 54. The sampling clock is also given to a discrete time equalizing filter 26 and an interpolated timing recovery 100. The recovery 100 generates a sampling value 102 interpolated in synchronization with a port rate by interpolating the equalized sampling value 32. A discrete time sequence detector 34 detects a binary sequence 33 estimated from the value 102. The recovery 100 also generates a data clock 104.
-
79.发明专利
公开(公告)号：JPH09219005A
公开(公告)日：1997-08-19
申请号：JP34431896
申请日：1996-12-24
Applicant: CIRRUS LOGIC INC
Inventor： ARAN JIEI AAMUSUTORONGU , KURISUTOFUAA PII ZUUKU
IPC: G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B19/04 , G11B20/10 , G11B20/18 , H03M13/00 , H03M13/15
Abstract: PROBLEM TO BE SOLVED: To obtain a compensation device in which complexity or redundancy is not remarkably increased without being affected by a software error by using a disappearance pointer for compensating influence of thermal asperity. SOLUTION: A thermal asperity(TA) detector 43 detects occurrence of thermal asperity by detecting saturation of an A/D sampling value 25 outputted by a sampling device 24. When occurrence of thermal asperity is detected, a pole of an AC coupling capacitor 55 is raised up through a line 46, loops of a timing recovery circuit 28, a gain controller 51 and a DC offset circuit 44 of a read-out channel is kept constant through a line 45, and a disappearance pointer is generated. And an on-the-fly error detector and correction circuit(EDAC) circuit process the disappearance pointer, and a discrete time sequence detector 34 corrects an error generated in a presumption digital sequence detected from the sampling value 25.
-
公开(公告)号：JPH09185361A
公开(公告)日：1997-07-15
申请号：JP31238696
申请日：1996-11-22
Applicant: CIRRUS LOGIC INC
Inventor： EGLIT ALEXANDER J
Abstract: PROBLEM TO BE SOLVED: To generate accurate pixel data which are scaled up or downsized by providing an interpolator which generates additional pixel data and an overwriting circuit which makes the interpolator generate additional pixel data from adjacent pixel data. SOLUTION: The interpolator 490 can generate additional pixel data by interpolating source video pixel on a current scan line with pixel data received through a line buffer output bus 398. A multiplexer 485 normally outputs pixel data on a previous scan line to an output bus 498, so the interpolator 490 generates additional pixel data from pixel data on the previous scan line. If, however, a slope overload state is present, the interpolator 490 can use >=1 adjacent pixel data instead of the pixel data on the current scan line.
-
-
-
-
-
-
-
-
-
Search Results
2192
records
(took 0.031 seconds)
