公开(公告)号：EP0779642A1

公开(公告)日：1997-06-18

申请号：EP95830520.3

申请日：1995-12-14

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Baldi, Livio ,  Tonti, Alessandro

IPC: H01J9/02

CPC classification number: H01J9/025 ,  H01J2201/319

Abstract: A process for forming a microtip cathode structure on a field emission display panel avoids the need of vacuum depositing a lift-off layer for the microtip deposition overstructure in specially equipped reactors to accomplish a deposition at a grazing angle, by co-patterning the lift-off layer together with an underlying metal grid layer by a succession of different etching steps through the openings of a grid definition mask. According to an embodiment, nickel is used as lift-off material and is either wet-etched or sputter-etched before performing a plasma etch of the underlying grid metal layer. According to an alternative embodiment the masking resist layer is used as lift-off material.

Abstract translation: 用于在场致发射显示面板上形成微尖端阴极结构的方法避免了在特别设计的反应器中真空沉积用于微尖端沉积过度结构的剥离层以实现掠射角的沉积的需要， 通过一系列通过网格定义掩模的开口的不同蚀刻步骤与底层金属网格层一起。 根据一个实施例，使用镍作为剥离材料，并且在对下面的栅极金属层进行等离子体蚀刻之前被湿式蚀刻或溅射蚀刻。 根据替代实施例，掩模抗蚀剂层用作剥离材料。

公开(公告)号：EP0655815B1

公开(公告)日：1997-06-04

申请号：EP93830484.7

申请日：1993-11-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Romano', Luigi ,  Magni, Pierangelo

IPC: H02G3/00 ,  H01L21/00 ,  B23K20/10

CPC classification number: H01L24/85 ,  B23K20/10 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

公开(公告)号：EP0772282A1

公开(公告)日：1997-05-07

申请号：EP95830456.0

申请日：1995-10-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Tassan Caser, Fabio ,  Dallabora, Marco ,  Defendi, Marco

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A negative charge pump circuit comprises: a plurality of charge pump stages (S1-S6), each charge pump stage (S1-S6) having an input node (I1-I6) and an output node (O1-O6) and comprising a pass transistor (P11-P16) and a first couplig capacitor (C21-C26), the pass transistor (P11-P16) having a first terminal connected to the input node (I1-I6), a second terminal connected to the output node (O1-O6) and a control terminal connected to an internal node (1-6) of the charge pump stage (S1-S6), said first coupling capacitor (C21-C26) having a first plate connected to said output node (O1-O6) and a second plate connected to a respective clock signal (A,B,C,D); negative voltage regulation means (7) for regulating a negative output voltage (V(O)) on an output node (O) of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit comprises at least one negative voltage limiting means (P7) electrically coupling said output node (O) of the negative charge pump circuit with the internal node (6) of the last charge pump stage (S6) of the negative charge pump circuit to limit the negative voltage on said internal node (6) and on the output node (O6) of said last charge pump stage (S6).

Abstract translation: 负电荷泵电路包括：多个电荷泵级（S1-S6），每个电荷泵级（S1-S6）具有输入节点（I1-I6）和输出节点（O1-O6）并且包括通过 晶体管（P11-P16）和第一耦合电容器（C21-C26），具有连接到输入节点（I1-I6）的第一端子的通过晶体管（P11-P16），连接到输出节点 -O6）和连接到电荷泵级（S1-S6）的内部节点（1-6）的控制端子，所述第一耦合电容器（C21-C26）具有连接到所述输出节点（O1-O6）的第一板 ）和连接到相应的时钟信号（A，B，C，D）的第二板; 负电压调节装置（7），用于调节负电荷泵电路的输出节点（O）上的负输出电压（V（O）），以提供固定的负电压值。 负电荷泵电路包括至少一个负电压限制装置（P7），将负电荷泵电路的输出节点（O）与负电荷的最后一个电荷泵级（S6）的内部节点（6）电耦合 泵电路以限制所述内部节点（6）和所述最后一个电荷泵级的输出节点（O6）上的负电压（S6）。

公开(公告)号：EP0772273A1

公开(公告)日：1997-05-07

申请号：EP95830458.6

申请日：1995-10-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Chiozzi, Giorgio

IPC: H02H9/00 ,  H03F1/52

CPC classification number: H03F1/523

Abstract: A sensor of instantaneous power dissipable through a power transistor (Pwr) of the MOS type connected between the output terminal (OUT) of a power stage and ground (GND). It comprises a MOS transistor (Q5) having its gate terminal connected to that of the power transistor, source terminal connected to ground, and drain terminal connected to a circuit node (N) which is coupled to the output terminal (OUT) by means of a current mirror circuit (D1,Q2) which includes a resistive element (R) in its input leg.
Connected to the circuit node is the base terminal of a bipolar transistor (Q4) which is respectively connected, through a diode (D3) and a constant current generator (Iref) between the output terminal and ground.

Abstract translation: 通过连接在功率级的输出端（OUT）和地（GND）之间的MOS型功率晶体管（Pwr）可以瞬时耗散的传感器。 它包括一个MOS晶体管（Q5），其栅极端子连接到功率晶体管的栅极端子，源极端子连接到地，而漏极端子连接到电路节点（N），该电路节点（N）借助于 在其输入支路中包括电阻元件（R）的电流镜电路（D1，Q2）。 连接到电路节点的是双极晶体管（Q4）的基极端子，分别通过二极管（D3）和输出端子与地之间的恒流发生器（Iref）连接。

公开(公告)号：EP0772246A1

公开(公告)日：1997-05-07

申请号：EP95830459.4

申请日：1995-10-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Bez, Roberto ,  Camerlenghi, Emilio

IPC: H01L29/92 ,  H01L29/94

CPC classification number: H01L28/40 ,  H01L29/94

Abstract: The invention relates to a high-capacitance capacitor (1) which is monolithically integratable on a semiconductor substrate (3) doped with a first type (P) of dopant and accomodating a diffusion well (4) which is doped with a second type (N) of dopant and has a first active region (5) formed therein.
A layer (6) of gate oxide is deposited over the diffusion well (4) which is covered with a first layer (POLY1) of polycrystalline silicon and separated from a second layer (POLY2) of polycrystalline silicon by an interpoly dielectric layer (7).
Advantageously, the high-capacitance capacitor (1) of the invention comprises a first capacitor element (C1) having the first (POLY1) and second (POLY2) layers of polycrystalline silicon as its conductive plates, and the interpoly dielectric layer (7) as the isolation dielectric, and a second capacitor element (C2) having the first layer (POLY1) of polycrystalline silicon and the diffusion well (4) as its conductive plates and the gate oxide layer (6) as the isolation dielectric.

Abstract translation: 本发明涉及一种高容量电容器（1），其可单片集成在掺杂有第一类型（P）掺杂剂的半导体衬底（3）上，并且容纳扩散阱（4），该扩散阱掺杂有第二类型（N ），并且其中形成有第一有源区（5）。 栅极氧化物层（6）沉积在扩散阱（4）上，扩散阱（4）被多晶硅的第一层（POLY1）覆盖，并通过多晶硅介电层（7）与多晶硅的第二层（POLY2）分离， 。 有利地，本发明的大容量电容器（1）包括具有第一（POLY1）和第二（POLY2）多晶硅层作为其导电板的第一电容器元件（C1），并且所述多晶硅绝缘层（7）为 隔离电介质和具有多晶硅的第一层（POLY1）和作为其导电板的扩散阱（4）和作为隔离电介质的栅极氧化物层（6）的第二电容器元件（C2）。

公开(公告)号：EP0772242A1

公开(公告)日：1997-05-07

申请号：EP95830454.5

申请日：1995-10-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Frisina, Ferruccio ,  Magri', Angelo ,  Ferla, Giuseppe

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66333

Abstract: A MOS technology power device comprises: a semiconductor material layer (2) of a first conductivity type; a conductive insulated gate layer (7,8,9) covering the semiconductor material layer (2); a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of an elongated body stripe, each elementary functional unit further comprising an elongated window (12) in the insulated gate layer (7,8,9) extending above the elongated body stripe (3). Each body stripe (3) includes at least one source portion (60;61;62) doped with dopants of the first conductivity type, intercalated with a body portion (40;41;3') of the body stripe (3) wherein no dopant of the first conductivity type are provided. The conductive insulated gate layer (7,8,9) comprises a first insulating material layer (7) placed above the semiconductor material layer (2), a conductive material layer (8) placed above the first insulating material layer (7), and a second insulating material layer (9) placed above the conductive material layer (8). Insulating material sidewall spacers (13) are provided to seal edges of the elongated window (12) in the insulated gate layer (7,8,9).

Abstract translation: MOS技术功率器件包括：第一导电类型的半导体材料层（2）; 覆盖半导体材料层（2）的导电绝缘栅极层（7,8,9）; 多个基本功能单元，每个单元功能单元包括形成在半导体材料层（2）中的第二导电类型的主体区域（3），具有细长主体条纹形式的主体区域（3），每个基本功能单元 功能单元还包括在所述细长主体条纹（3）上方延伸的所述绝缘栅极层（7,8,9）中的细长窗口（12）。 每个体条纹（3）包括掺杂有第一导电类型的掺杂剂的至少一个源极部分（60; 61; 62），其插入本体条纹（3）的主体部分（40; 41; 3'），其中不 提供第一导电类型的掺杂剂。 导电绝缘栅层（7,8,9）包括置于半导体材料层（2）上方的第一绝缘材料层（7），置于第一绝缘材料层（7）上方的导电材料层（8），以及 放置在导电材料层（8）上方的第二绝缘材料层（9）。 提供绝缘材料侧壁间隔件（13）以密封绝缘栅极层（7,8,9）中的细长窗口（12）的边缘。

公开(公告)号：EP0768758A1

公开(公告)日：1997-04-16

申请号：EP95830430.5

申请日：1995-10-12

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Gaibotti, Maurizio ,  Adduci, Francesco

IPC: H03K3/3562

CPC classification number: H03K3/35625

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section (100) and a slave section (200); the master section comprises a master latch structure (5) and the slave section comprises a slave latch structure (6); the master structure (100) and the slave structure (100) are interposed between a power supply line (V DD ) and a ground line (7), and each structure is constituted by a first pair of transistors (8, 9; 12, 13) and by a second pair of transistors (10, 11; 14, 15). The particularity of the invention is that in the master latch structure (5) the transistors (8, 9) the source terminals whereof are connected to the power supply line (V DD ) and constitute a first one of the two pairs of transistors (8, 9; 10, 11) are P-channel MOS transistors, the source terminals of the second pair of transistors (10, 11) of the master latch structure (5) are connected to the respective drain terminals of an additional pair of transistors (24, 25), the source terminals whereof are connected to the ground line (7); same-phase clock signals (CK) are fed both to the master section (100) and to the slave section (200).

Abstract translation: 低消耗和高密度D触发器电路实现，特别是用于标准单元库，它包括一个主部分（100）和从段（200）; 主部分包括主锁存器结构（5）和从动部分包括从锁存器结构（6）; 主结构（100）和从结构（100）被一个电源线（VDD）和接地线（7）之间，并且每个结构是由第一对晶体管（8,9构成; 12,13 ），并用第二对晶体管（10，11的14，15）。 本发明的特殊性是在主锁存器结构（5）的晶体管那样（8,9）的源极端WHEREOF被连接到电源线（VDD），并构成两对晶体管中的第一个（8， 9; 10，11）是主锁存器结构（5）被连接到另外的一对晶体管的所述respectivement漏极端子的P沟道MOS晶体管，所述第二对晶体管（10的源极端子，11）（24 ，25），则源终端WHEREOF被连接到接地线（7）; 同相时钟信号（CK）被馈送到两个主部（100）和向从属部（200）。

公开(公告)号：EP0768610A1

公开(公告)日：1997-04-16

申请号：EP95830433.9

申请日：1995-10-13

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Fabbrizio, Vito ,  Colli, Gianluca ,  Kramer, Alan

IPC: G06F15/80 ,  G06G7/60

CPC classification number: G06N3/063 ,  G06N3/0635

Abstract: A neural network (1) including a number of synaptic weighting elements (15, 17), and a neuron stage (5); each of the synaptic weighting elements (15, 17) having a respective synaptic input connection (11, 13) supplied with a respective input signal (x 1 , ..., x n ); and the neuron stage (5) having inputs (36, 37) connected to the synaptic weighting elements, and being connected to an output (39) of the neural network (1) supplying a digital output signal (O). The synaptic weighting elements (15, 17) are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage (5) provides for measuring conductance (33-35, 43-45) on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract translation: 包括许多突触加权元素（15,17）和神经元阶段（5）的神经网络（1）; 每个突触加权元件（15,17）具有各自的输入信号（x1，...，xn）的突触输入连接（11,13）; 和具有与突触加权元件连接的输入端（36,37）的神经元级（5），并连接到提供数字输出信号（O）的神经网络（1）的输出端（39）。 突触加权元件（15,17）由可编程为不同阈值电压电平的存储器单元形成，使得每个呈现相应的可编程电导; 并且神经元阶段（5）基于通过存储器单元的电流提供测量电导（33-35,43-45），并且基于突触元件的总电导产生二进制输出信号。

公开(公告)号：EP0429829B1

公开(公告)日：1997-04-09

申请号：EP90119872.1

申请日：1990-10-17

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Gola, Alberto ,  Alzati, Angelo ,  Novelli, Aldo

IPC: H03K5/24 ,  H03F3/45

CPC classification number: H03F3/4508 ,  H03F3/45076 ,  H03F3/45179 ,  H03F3/45286 ,  H03F3/45291 ,  H03F2203/45028 ,  H03F2203/45144 ,  H03F2203/45188 ,  H03F2203/45304 ,  H03F2203/45612 ,  H03K5/2445

公开(公告)号：EP0763887A1

公开(公告)日：1997-03-19

申请号：EP95830377.8

申请日：1995-09-14

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruccoleri, Melchiorre ,  Demicheli, Davide ,  Demicheli, Marco ,  Patti, Giuseppe

IPC: H03G1/00 ,  H03G3/20 ,  G11B5/02

CPC classification number: H03G3/3026 ,  G11B5/02 ,  H03G1/0088

Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators.
The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

Abstract translation: 所描述的电路包括连接到差分放大器（VGA）的输出的双半波整流器（DHWR），以便产生取决于放大器（VGA）的输出信号的半波幅度的两个量， 每个具有连接到整流器（DHWR）的输出（OUT1，OUT2）和参考输入（IN-1，IN-2）的输入（IN + 1，IN + 2））的两个比较器（COMP1，COMP2） 当各个半波的振幅大于施加到参考输入（IN-1，IN-2）的电平时，产生相应的输出信号，并且处理装置（Str1，A1，R1，Str2，A2，R2， C），用于根据两个比较器的输出信号的持续时间产生用于调节放大器的增益的信号。 当待放大的信号（v +，v-）不对称时，可以有利地使用该电路。