公开(公告)号：EP0782148A3

公开(公告)日：1999-04-14

申请号：EP96830245.5

申请日：1996-04-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Dallabora, Marco ,  Villa, Corrado ,  Bartoli, Simone ,  Defendi, Marco

IPC: G11C16/06

CPC classification number: G11C16/344 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459

Abstract: The invention concerns a method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which comprises a matrix of memory cells divided into sectors and programmable in a byte mode. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied. The invention further provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.

公开(公告)号：EP0772200A1

公开(公告)日：1997-05-07

申请号：EP95830461.0

申请日：1995-10-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Tassan Caser, Fabio ,  Dellabora, Marco ,  Defendi, Marco

IPC: G11C16/06 ,  H02M3/07

CPC classification number: H02M3/073 ,  G11C16/12 ,  G11C16/30 ,  H02M3/07 ,  H03K3/0315

Abstract: The present invention relates to a voltage (hv) generator (4) for electrically programmable non-volatile memory cells (2), being of a type which comprises a plurality of charge pump circuits (11A,11B) having inputs controlled by a plurality of phase generators (9) and outputs connected to an output terminal (OUT) of the voltage generator (4), the charge pump circuits (11A,11B) being laid as pairs (11) of first (11A) and second (11B) charge pump circuits, and the first charge pump circuits (11A) being active when the second charge pump circuits (11B) are inactive, and vice versa.
The invention also concerns a charge pump circuit, a phase generator (9) and a clock generator circuit (7) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2).

Abstract translation: 本发明涉及一种用于电可编程非易失性存储器单元（2）的电压（hv）发生器（4），它是一种类型，它包括多个电荷泵电路（11A，11B），其具有由多个 相位发生器（9）和连接到电压发生器（4）的输出端子（OUT）的输出，电荷泵电路（11A，11B）被布置为第一（11A）和第二（11B）充电对（11） 泵电路，并且当第二电荷泵电路（11B）不活动时，第一电荷泵电路（11A）有效，反之亦然。 本发明还涉及用于电可编程非易失性存储器单元（2）的矩阵阵列的编程电路的电荷泵电路，相位发生器（9）和时钟发生器电路（7）。

公开(公告)号：EP0675440A1

公开(公告)日：1995-10-04

申请号：EP94830146.0

申请日：1994-03-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pascucci, Luigi ,  Carrera, Marcello ,  Defendi, Marco

IPC: G06F11/20

CPC classification number: G11C29/80 ,  G11C5/025

Abstract: A Redundancy circuitry layout for a semiconductor memory device comprises an array (MAR) of programmable non-volatile memory elements (TF0,TF1) for storing the addresses of defective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines; the redundancy circuitry layout is divided in identical layout strips (LS1-LS4) which are perpendicular to the array (MAR) of memory elements (TF0,TF1) and which comprise each a first and a second strip sides located at opposite sides of the array (MAR) of memory elements (TF0,TF1), the first strip side containing at least one programmable non-volatile memory register (CRRA,CRRB) of a first plurality for the selection of redundancy bit lines and being crossed by a column address signal bus (CABUS) running parallel to the array (MAR of memory elements (TF0,TF1), the second strip side containing one programmable non-volatile memory register (RRR) of a second plurality for the selection of redundancy word lines and being crossed by a row address signal bus (RABUS) running parallel to the array (MAR) of memory elements (TF0,TF1).

Abstract translation: 用于半导体存储器件的冗余电路布局包括可编程非易失性存储器元件（TF0，TF1）的阵列（MAR），用于存储必须由冗余位线和字分别功能地替换的有缺陷位线和字线的地址 线; 冗余电路布局被分成与存储元件（TF0，TF1）的阵列（MAR）垂直的相同的布局条（LS1-LS4），并且它们包括位于阵列的相对侧的第一和第二条边 （TF0，TF1）的第一条带侧（MAR），第一条带侧包含用于选择冗余位线的第一多个可编程非易失性存储器寄存器（CRRA，CRRB），并被列地址信号 总线（CABUS）平行于阵列（存储元件（TF0，TF1）的MAR），第二条带侧包含用于选择冗余字线的第二多个可编程非易失性存储器寄存器（RRR），并被 与存储元件（TF0，TF1）的阵列（MAR）并行运行的行地址信号总线（RABUS）。

公开(公告)号：EP0845784A1

公开(公告)日：1998-06-03

申请号：EP96830598.7

申请日：1996-11-27

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Villa, Corrado ,  Defendi, Marco ,  Bettini, Luigi

IPC: G11C8/00

CPC classification number: G11C8/18

Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) in order to control the reading phase of memorycells in semiconductor integrated, electronic memory devices. The pulse signal (ATD) is generated upon sensing a change in logic state on at least one of a plurality of address input terminals (PAD) of the memory cells to also generate an equalization signal (EQLZ) for a sense amplifier.
The logic state of said pulse signal (ATD) is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal (EQLZ). To this aim, a re-acknowledge circuit portion (15) is provided which is input a corresponding signal to the equalization signal (EQLZ) and feedback connected to the output node (12) to drive the discharging of the node (12) with a predetermined delay from the reception of the input signal.

Abstract translation: 本发明涉及一种用于产生脉冲同步信号（ATD）的方法和电路，以便控制半导体集成的电子存储器件中存储单元的读取相位。 在感测存储器单元的多个地址输入端（PAD）中的至少一个上的逻辑状态的变化时产生脉冲信号（ATD），以生成用于读出放大器的均衡信号（EQLZ）。 所述脉冲信号（ATD）的逻辑状态由具有预定延迟的反馈响应重新确认，并且在接收到所述均衡信号（EQLZ）的相应信号时产生。 为此目的，提供了一个重新确认电路部分（15），其向均衡信号（EQLZ）输入相应的信号，并且连接到输出节点（12）的反馈以使得节点（12）的放电以 从接收输入信号的预定延迟。

公开(公告)号：EP0782148A2

公开(公告)日：1997-07-02

申请号：EP96830245.5

申请日：1996-04-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Dallabora, Marco ,  Villa, Corrado ,  Bartoli, Simone ,  Defendi, Marco

IPC: G11C16/06

CPC classification number: G11C16/344 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459

Abstract: The invention concerns a method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which comprises a matrix of memory cells divided into sectors and programmable in a byte mode. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied.
The invention further provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.

Abstract translation: 本发明涉及在编程和电可编程的擦除的步骤避免干扰的方法，半导体集成电路的非易失性存储器装置，其包括存储器单元分成扇区和可编程以字节模式的矩阵。 的字节的内容的操作验证要被编程，对于每个单独的位被执行时，第一编程脉冲施加之前就被设置。 本发明还提供了几个扇区的期间擦除步骤的擦除并行，并为矩阵中的每个扇区的擦除步骤的验证。 如果验证表明做了一个部门被擦除，该行业是应用没有进一步的擦除脉冲。

公开(公告)号：EP0772282A1

公开(公告)日：1997-05-07

申请号：EP95830456.0

申请日：1995-10-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Tassan Caser, Fabio ,  Dallabora, Marco ,  Defendi, Marco

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A negative charge pump circuit comprises: a plurality of charge pump stages (S1-S6), each charge pump stage (S1-S6) having an input node (I1-I6) and an output node (O1-O6) and comprising a pass transistor (P11-P16) and a first couplig capacitor (C21-C26), the pass transistor (P11-P16) having a first terminal connected to the input node (I1-I6), a second terminal connected to the output node (O1-O6) and a control terminal connected to an internal node (1-6) of the charge pump stage (S1-S6), said first coupling capacitor (C21-C26) having a first plate connected to said output node (O1-O6) and a second plate connected to a respective clock signal (A,B,C,D); negative voltage regulation means (7) for regulating a negative output voltage (V(O)) on an output node (O) of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit comprises at least one negative voltage limiting means (P7) electrically coupling said output node (O) of the negative charge pump circuit with the internal node (6) of the last charge pump stage (S6) of the negative charge pump circuit to limit the negative voltage on said internal node (6) and on the output node (O6) of said last charge pump stage (S6).

Abstract translation: 负电荷泵电路包括：多个电荷泵级（S1-S6），每个电荷泵级（S1-S6）具有输入节点（I1-I6）和输出节点（O1-O6）并且包括通过 晶体管（P11-P16）和第一耦合电容器（C21-C26），具有连接到输入节点（I1-I6）的第一端子的通过晶体管（P11-P16），连接到输出节点 -O6）和连接到电荷泵级（S1-S6）的内部节点（1-6）的控制端子，所述第一耦合电容器（C21-C26）具有连接到所述输出节点（O1-O6）的第一板 ）和连接到相应的时钟信号（A，B，C，D）的第二板; 负电压调节装置（7），用于调节负电荷泵电路的输出节点（O）上的负输出电压（V（O）），以提供固定的负电压值。 负电荷泵电路包括至少一个负电压限制装置（P7），将负电荷泵电路的输出节点（O）与负电荷的最后一个电荷泵级（S6）的内部节点（6）电耦合 泵电路以限制所述内部节点（6）和所述最后一个电荷泵级的输出节点（O6）上的负电压（S6）。

公开(公告)号：EP0675440B1

公开(公告)日：1998-08-05

申请号：EP94830146.0

申请日：1994-03-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Carrera, Marcello ,  Defendi, Marco

IPC: G06F11/20

CPC classification number: G11C29/80 ,  G11C5/025

公开(公告)号：EP0806773A1

公开(公告)日：1997-11-12

申请号：EP96830267.9

申请日：1996-05-09

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Dallabora, Marco ,  Villa, Corrado ,  Defendi, Marco

IPC: G11C29/00

CPC classification number: G11C29/24 ,  G11C29/02 ,  G11C29/44 ,  G11C29/824

Abstract: An electrically erasable and programmable non-volatile memory device comprises at least one memory sector (S1-S8) comprising an array of memory cells (MC) arranged in rows (WL0-WL255) and first-level columns (BL0-BL255), the first-level columns (BL0-BL255) being grouped together in groups of first-level columns each coupled to a respective second-level column (B1-B64), first-level selection means (2) for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means (3,4) for selecting one of the second-level columns, first direct memory access test means (SW6) activatable in a first test mode for directly coupling a selected memory cell (MC) of the array to a respective output terminal (Oi) of the memory device, redundancy columns (RBL0-RBL3) of redundancy memory cells (RMC) for replacing defective columns (BL0-BL255) of memory cells (MC), and a redundancy control circuit (CAM1-CAM4,5-7,12,SW1-SW5,24) comprising defective-address storage means (CAM1-CAM4) for storing addresses of the defective columns (BL0-BL255) and activating respective redundancy columns (RBL0-RBL3) when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means (24) activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements (AB0-AB7,GB) of the defective-address storage means (CAM1-CAM4) to respective second-level columns (B1-B64) of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals (Oi) of the memory device.

Abstract translation: 电可擦除可编程的非易失性存储器件包括至少一个存储器扇区（S1-S8），其包括以行（WL0-WL255）和第一级列（BL0-BL255）排列的存储器单元阵列（MC） 第一级列（BL0-BL255）被分组在一起，每一列分别耦合到相应的第二级列（B1-B64），第一级选择装置（2）用于选择性地耦合一个第一级列 对于每个组到各个第二级列，用于选择第二级列之一的第二级选择装置（3,4），在第一测试模式中可激活的第一直接存储器访问测试装置（SW6），用于直接耦合 阵列的选择存储单元（MC）到存储器件的相应输出端（Oi），冗余存储单元（RMC）的冗余列（RBL0-RBL3）用于替换存储器单元（MC）的缺陷列（BL0-BL255） ）和包括有缺陷的冗余控制电路（CAM1-CAM4,5-7,12，SW1-SW5,24） 用于存储有缺陷列（BL0-BL255）的地址并激活各个冗余列（RBL0-RBL3）的地址存储装置（CAM1-CAM4）。 冗余控制电路包括第二直接存储器访问测试装置（24），其与第一直接存储器存取测试装置一起可激活第二测试模式，用于将缺陷地址存储装置（CAM1）的存储元件（AB0-AB7，GB）直接耦合 -CAM4）到阵列的各个第二级列（B1-B64），从而可以将缺陷地址存储装置的存储元件直接耦合到存储器件的输出端（Oi）。

公开(公告)号：EP0782145A1

公开(公告)日：1997-07-02

申请号：EP95830554.2

申请日：1995-12-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Villa, Corrado ,  Defendi, Marco ,  Bettini, Luigi

IPC: G11C11/00

CPC classification number: G11C16/16

Abstract: The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps:

erasing some or all of the matrix sectors in parallel;
subsequently reading and checking each erased sector;
storing the address of a sector being checked when the issue of a check is unfavorable;
carrying out a fresh parallel erasing step; and
starting a new reading/checking step from the sector that has checked unfavorably.

Abstract translation: 本发明涉及擦除被构造为多扇区矩阵存储器并且具有集成到该器件中的擦除算法的类型的电可编程非易失性存储器件的方法。 该方法包括以下步骤：并行擦除部分或全部矩阵扇区; 随后读取和检查每个已擦除的扇区; 当支票的发行不利时，存储被检查的部门的地址; 执行新的并行擦除步骤; 并从不利地检查的部门开始新的阅读/检查步骤。