公开(公告)号：KR100385954B1

公开(公告)日：2003-06-02

申请号：KR1020010004223

申请日：2001-01-30

Applicant: 삼성전자주식회사

Inventor： 양원석 ,  황유상 ,  김기남 ,  정홍식

IPC: H01L27/10

CPC classification number: H01L21/76897 ,  H01L21/76829 ,  H01L21/76834 ,  H01L27/10882 ,  H01L27/10894

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract translation: 蚀刻停止层以选择性的方式选择性地设置在多层电路的层之间，以允许在随后的制造工艺期间杂质的除气。 蚀刻停止层形成在下面的柱上，以便在上层中形成的上面的柱中形成对准目标。 以这种方式，可以以相对密集的配置来制造多层电路，例如存储器设备。

公开(公告)号：KR1020030001217A

公开(公告)日：2003-01-06

申请号：KR1020020006192

申请日：2002-02-04

Applicant: 삼성전자주식회사

Inventor： 남상돈 ,  이규만 ,  김현호 ,  정동진 ,  김기남

IPC: H01L27/105

Abstract: PURPOSE: A ferroelectric memory device having an extended plate line and a method for fabricating the same are provided to maximize a contact area between a plate line and an upper electrode and improve an insulating characteristic between the plate line and a main word line. CONSTITUTION: An isolation layer(53) is formed on a semiconductor substrate(51). A plurality of insulated gate electrodes(57) are formed across the isolation layer(53). An active region is divided into one common drain region(61d) and two source regions(61s). A lower interlayer dielectric(74) is deposited on a whole surface of the above structure. A plurality of contact plugs(75) are connected with the source regions(61s). A ferroelectric capacitor(82) is arranged on the whole surface of the above structure. The ferroelectric capacitor(82) includes a lower electrode(77), a ferroelectric layer pattern(79), and an upper electrode(81). An insulating layer pattern(85a) are formed on a gap region between the ferroelectric capacitors(82). A local plate line(87) is formed on the ferroelectric capacitor(82) and the insulating layer pattern(85a). The first and the second upper interlayer dielectric(89,93) are deposited thereon. A main word line(91) is inserted between the first and the second upper interlayer dielectric(89,93). A main plate line(97) is connected with the local plate line(87) through a slit type via hole(95).

Abstract translation: 目的：提供具有延长板线的铁电存储器件及其制造方法，以使板线与上电极之间的接触面积最大化，并提高板线与主字线之间的绝缘特性。 构成：在半导体衬底（51）上形成隔离层（53）。 跨隔离层（53）形成多个绝缘栅电极（57）。 有源区被分为一个公共漏极区（61d）和两个源极区（61s）。 在上述结构的整个表面上沉积下层间电介质（74）。 多个接触插塞（75）与源极区域（61s）连接。 铁电电容器（82）布置在上述结构的整个表面上。 铁电电容器（82）包括下电极（77），铁电层图案（79）和上电极（81）。 绝缘层图案（85a）形成在铁电电容器（82）之间的间隙区域上。 在铁电电容器（82）和绝缘层图案（85a）上形成有局部板线（87）。 第一和第二上层间电介质（89,93）沉积在其上。 主字线（91）插入在第一和第二上层间电介质（89,93）之间。 主板线（97）通过狭缝型通孔（95）与局部板线（87）连接。

公开(公告)号：KR100351055B1

公开(公告)日：2002-09-05

申请号：KR1020000035707

申请日：2000-06-27

Applicant: 삼성전자주식회사

Inventor： 고관협 ,  김기남

IPC: H01L27/10

Abstract: 게이트 전극에 의하여 자기정렬되는 셀프얼라인 콘택 플러그를 갖춘 반도체 메모리 소자의 제조 공정에서 트랜지스터의 문턱 전압을 조절하기 위한 채널 이온 주입 공정을 포함하는 반도체 메모리 소자의 제조 방법에 관하여 개시한다. 본 발명에 따른 반도체 메모리 소자의 제조 방법에서는 게이트 전극을 형성하기 위한 제1 부분과, 비트 라인 콘택을 형성하기 위한 제2 부분과, 커패시터의 스토리지 노드 콘택을 형성하기 위한 제3 부분을 포함하는 활성 영역이 정의된 반도체 기판에서 상기 제1 부분 및 제2 부분 만을 노출시키도록 상기 반도체 기판 상면을 덮는 마스크 패턴을 이용한다. 본 발명에 따른 반도체 메모리 소자의 제조 방법에서는 게이트 전극을 형성하기 위한 제1 부분과, 비트 라인 콘택을 형성하기 위한 제2 부분과, 커패시터의 스토리지 노드 콘택을 형성하기 위한 제3 부분을 포함하는 활성 영역을 반도체 기판상에 정의한다. 상기 마스크 패턴을 이온 주입 마스크로 하여 상기 반도체 기판의 활성 영역에 제1 도전형의 도판트를 이온 주입하여 상기 제1 부분 및 제2 부분에만 트랜지스터의 문턱 전압 조절을 위한 채널 이온 주입 영역을 형성한다.

公开(公告)号：KR1020020066568A

公开(公告)日：2002-08-19

申请号：KR1020010006813

申请日：2001-02-12

Applicant: 삼성전자주식회사

Inventor： 김기남 ,  송윤종

IPC: H01L27/105

CPC classification number: H01L27/11502 ,  H01L21/3144 ,  H01L21/3185 ,  H01L21/76895 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

Abstract: PURPOSE: A ferroelectric memory device and a method for forming the same are provided to improve integration and obtain a stable contact resistance of the ferroelectric memory device. CONSTITUTION: A transistor(204) including a source region(206b) and a drain region(206a) is formed on an active region of a substrate(200). The first interlayer dielectric(208) is formed on the substrate(200) and the transistor(204). The first contact holes(210a,210b) are formed in the first interlayer dielectric(208). A bit line(212a) and a buried contact structure(212b) are arranged on the first interlayer dielectric(208). The second interlayer dielectric(216) is formed thereon. A ferroelectric capacitor(226) is formed on the second interlayer dielectric(216). The second contact hole(218) is formed in the second interlayer dielectric(216). An oxygen diffusion barrier is formed on the first interlayer dielectric(208). The third interlayer dielectric(230) is formed on the ferroelectric capacitor(226) and the second interlayer dielectric(216). The first wire(232) is formed on the third interlayer dielectric(230). An insulating layer(234) is formed on the third interlayer dielectric(230). The second wire(238) is formed on the insulating layer(234). A passivation layer is formed on the insulating layer(234) and the second wire(238).

Abstract translation: 目的：提供铁电存储器件及其形成方法，以提高集成度并获得稳定的铁电存储器件的接触电阻。 构成：在衬底（200）的有源区上形成包括源极区（206b）和漏极区（206a）的晶体管（204）。 第一层间电介质（208）形成在衬底（200）和晶体管（204）上。 第一接触孔（210a，210b）形成在第一层间电介质（208）中。 位线（212a）和掩埋接触结构（212b）布置在第一层间电介质（208）上。 在其上形成第二层间电介质（216）。 铁电电容器（226）形成在第二层间电介质（216）上。 第二接触孔（218）形成在第二层间电介质（216）中。 在第一层间电介质（208）上形成氧扩散阻挡层。 第三层间电介质（230）形成在强电介质电容器（226）和第二层间电介质（216）上。 第一导线（232）形成在第三层间电介质（230）上。 绝缘层（234）形成在第三层间电介质（230）上。 第二线（238）形成在绝缘层（234）上。 在绝缘层（234）和第二导线（238）上形成钝化层。

公开(公告)号：KR1020020065983A

公开(公告)日：2002-08-14

申请号：KR1020010006123

申请日：2001-02-08

Applicant: 삼성전자주식회사

Inventor： 양원석 ,  김기남 ,  정홍식

IPC: H01L21/28

CPC classification number: H01L23/485 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor device having a multi-layered interconnection structure is provided to prevent a short-circuit between a landing pad and a circuit pattern, by forming a step-type contact stud, by forming a pillar-type contact stud in an interlayer dielectric and by forming a conductive pattern for a landing pad on the interlayer dielectric such that the conductive pattern is of a size greater than the line width of the contact stud. CONSTITUTION: The interlayer dielectric is formed on a semiconductor substrate(200). The first contact stud is formed in the interlayer dielectric, in which the line width of an inlet part adjacent to the surface of the interlayer dielectric is greater than that of a contact part adjacent to the substrate. The second stud is formed in the interlayer dielectric, separated from the first contact stud by a predetermined interval.

Abstract translation: 目的：提供具有多层互连结构的半导体器件，以通过在层间电介质中形成柱状接触柱来形成台阶式接触柱，以防止接地焊盘和电路图案之间的短路 并且通过在层间电介质上形成用于着陆焊盘的导电图案，使得导电图案的尺寸大于接触柱的线宽度。 构成：层间电介质形成在半导体衬底（200）上。 第一接触柱形成在层间电介质中，其中与层间电介质的表面相邻的入口部分的线宽大于与衬底相邻的接触部分的线宽。 第二螺柱形成在层间电介质中，以预定的间隔与第一接触柱分开。

公开(公告)号：KR1020020033484A

公开(公告)日：2002-05-07

申请号：KR1020010004222

申请日：2001-01-30

Applicant: 삼성전자주식회사

Inventor： 정홍식 ,  양원석 ,  김기남

IPC: H01L27/10

CPC classification number: H01L27/10894 ,  H01L27/10855

Abstract: PURPOSE: A semiconductor device having a bit line landing pad and a borderless contact on a bit line stud having an etch stop layer is provided to guarantee precision of an etch depth, by forming the etch stop layer on the stud of a lower layer such that the etch stop layer has etch selectively different from that of a lower insulation layer. CONSTITUTION: The first stud is formed in the first insulation layer(58). The etch stop layer(68) is formed on the first stud. The second insulation layer is formed on the etch stop layer. The second stud passes through the second insulation layer and the etch stop layer, electrically connected to the first stud. The etch stop layer has a different etch selectivity from that of the second insulation layer.

Abstract translation: 目的：提供具有位线着陆焊盘和位于具有蚀刻停止层的位线螺柱上的无边界触点的半导体器件，以通过在较低层的螺柱上形成蚀刻停止层来确保蚀刻深度的精度，使得 蚀刻停止层具有与下绝缘层的蚀刻选择性不同的蚀刻。 构成：第一螺柱形成在第一绝缘层（58）中。 蚀刻停止层（68）形成在第一螺柱上。 第二绝缘层形成在蚀刻停止层上。 第二螺柱穿过电连接到第一螺柱的第二绝缘层和蚀刻停止层。 蚀刻停止层具有与第二绝缘层的蚀刻选择性不同的蚀刻选择性。

公开(公告)号：KR1020020001263A

公开(公告)日：2002-01-09

申请号：KR1020000035707

申请日：2000-06-27

Applicant: 삼성전자주식회사

Inventor： 고관협 ,  김기남

IPC: H01L27/10

CPC classification number: H01L27/10873 ,  H01L21/823425 ,  H01L21/823481

Abstract: PURPOSE: A method for fabricating a semiconductor memory device using a mask pattern for implanting channel ions is provided to control a threshold voltage of a transistor by performing a channel ion implantation process. CONSTITUTION: An isolation region(102) is formed on a semiconductor substrate(100). A well and a channel stop layer(106) are formed on a semiconductor substrate(100). An ion implantation mask pattern including an opening is formed on an active region of the semiconductor substrate(100). A channel ion implantation region(122) is formed by implanting p-type dopants into the semiconductor substrate(100). A gate electrode(130) is formed on the active region. A nitride layer spacer(134) is formed at the gate electrode(130) and a sidewall of a silicon nitride layer pattern(132). Source/drain regions(142a,142b) are formed on the active region. A contact plug(150a) connected with the source/drain region(142a) and a contact plug(150b) connected with the source/drain region(142b) are formed on the active region.

Abstract translation: 目的：提供一种使用掩模图案制造用于注入通道离子的半导体存储器件的方法，以通过执行沟道离子注入工艺来控制晶体管的阈值电压。 构成：在半导体衬底（100）上形成隔离区（102）。 阱和沟道阻挡层（106）形成在半导体衬底（100）上。 在半导体衬底（100）的有源区上形成包括开口的离子注入掩模图案。 通过将p型掺杂剂注入到半导体衬底（100）中来形成通道离子注入区（122）。 在有源区上形成栅电极（130）。 在栅电极（130）和氮化硅层图案（132）的侧壁上形成氮化物层间隔物（134）。 源极/漏极区（142a，142b）形成在有源区上。 与源极/漏极区域（142a）连接的接触插塞（150a）和与源极/漏极区域（142b）连接的接触插塞（150b）形成在有源区域上。

公开(公告)号：KR1020010045595A

公开(公告)日：2001-06-05

申请号：KR1019990048931

申请日：1999-11-05

Applicant: 삼성전자주식회사

Inventor： 우형수 ,  송상호 ,  김기남

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/90

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to improve step coverage in a region between a cell region and a core/peripheral region, by maintaining a doped polysilicon layer for a plate electrode near the core/peripheral region. CONSTITUTION: A cell region and a core/peripheral region are defined in a semiconductor substrate(100). A doped polysilicon layer(206,304) for a capacitor plate electrode having a gate line is formed on the entire surface of the cell region and the core/peripheral region. The doped polysiliconlayer in the cell region is etched to form an opening, wherein the inner wall of the opening becomes a plate electrode. After a dielectric layer(300) is formed on the inner wall of the opening, a storage node of a spacer type is formed on the dielectric layer on the inner wall of the opening by a self-aligned method. Therefore, a capacitor composed of the plate electrode, the dielectric layer and the storage node is formed.

Abstract translation: 目的：提供一种用于制造半导体器件的电容器的方法，以通过在芯/周边区域附近保持用于板电极的掺杂多晶硅层来改善单元区域和芯/外围区域之间的区域中的台阶覆盖。 构成：在半导体衬底（100）中限定单元区域和芯/外围区域。 在电池区域和芯/周边区域的整个表面上形成用于具有栅极线的电容器极板电极的掺杂多晶硅层（206,304）。 蚀刻单元区域中的掺杂多晶硅层以形成开口，其中开口的内壁变成平板电极。 在开口的内壁上形成有电介质层（300）之后，通过自对准方法在开口的内壁上的电介质层上形成隔离物的存储节点。 因此，形成由平板电极，电介质层和存储节点构成的电容器。

公开(公告)号：KR1020010036018A

公开(公告)日：2001-05-07

申请号：KR1019990042852

申请日：1999-10-05

Applicant: 삼성전자주식회사

Inventor： 정홍식 ,  김기남

IPC: H01L27/108

Abstract: PURPOSE: A method for manufacturing a bitline contact of a semiconductor device is provided to form stable metal silicide layers in different regions, by forming a silicon supply layer inside a contact hole before a metal layer for forming the silicide layer is manufactured. CONSTITUTION: A plurality of the first and second transistors having at least a gate electrode(120,140) composed of polysilicon/tungsten silicide are formed on a semiconductor substrate(100) in which a cell array region and a peripheral region are defined. The first interlayer dielectric(220) is formed on the substrate including the plurality of the first and second transistors. A conductive pad is formed among the plurality of the first transistors. The second interlayer dielectric(260) is formed on the first interlayer dielectric, the conductive pad and the first and second transistors. The second interlayer dielectric is etched to form the first, second and third bitline contact holes(280a,280b,280c) exposing the conductive pad, the substrate on both sides of the second transistors and the tungsten silicide layer, respectively. A silicon supply layer(300) is formed in the second interlayer dielectric and the bitline contact hole. A metal layer(320) for forming silicide is deposited and annealed on the silicon supply layer to form a metal silicide layer. A barrier metal layer is formed on the silicide layer. A bitline metal layer is formed on the barrier metal layer.

Abstract translation: 目的：提供一种用于制造半导体器件的位线接触的方法，以在制造用于形成硅化物层的金属层之前在接触孔内形成硅供应层，以在不同区域中形成稳定的金属硅化物层。 构成：在其中限定了电池阵列区域和外围区域的半导体衬底（100）上形成至少具有由多晶硅/硅化钨构成的栅电极（120,140）的多个第一和第二晶体管。 在包括多个第一和第二晶体管的基板上形成第一层间电介质（220）。 在多个第一晶体管中形成导电焊盘。 第二层间电介质（260）形成在第一层间电介质，导电焊盘和第一和第二晶体管上。 蚀刻第二层间电介质以形成分别暴露导电焊盘，第二晶体管两侧的衬底和硅化钨层的第一，第二和第三位线接触孔（280a，280b，280c）。 在第二层间电介质和位线接触孔中形成硅供给层（300）。 用于形成硅化物的金属层（320）在硅供应层上沉积并退火以形成金属硅化物层。 在硅化物层上形成阻挡金属层。 在阻挡金属层上形成位线金属层。

公开(公告)号：KR100285701B1

公开(公告)日：2001-04-02

申请号：KR1019980025174

申请日：1998-06-29

Applicant: 삼성전자주식회사

Inventor： 김기남 ,  심재훈 ,  이재규

IPC: H01L21/28

Abstract: 본 발명은 선택되지 않은 셀(non-selected cell)의 스토리지 노드의 퍼텐셜(potential)에 의한 선택된 셀(selected cell)의 문턱 전압(threshold voltage) 변화를 방지하는 트렌치 격리의 제조 방법 및 그 구조에 관한 것으로, 트렌치 하부면 및 양측벽에 손상층을 제거하기 위한 열산화막이 형성된 후, 트렌치를 완전히 채울 때까지 도핑된 폴리실리콘 내지 고온 융점(high temperature melting point)을 갖는 금속 등의 물질층이 증착 된다. 물질층의 상부 표면이 반도체 기판의 상부 표면 보다 낮아지도록 물질층이 리세스(recess)된 후, 리세스된 부위를 채우도록 트렌치 격리막이 증착 된다. 이때, 후속 공정에서 물질층이 노출되는 것을 방지하기 위해 물질층과 트렌치 격리막 사이에 실리콘 질화막이 형성될 수 있다. 이와 같은 반도체 장치 및 그의 제조 방법에 의해서, 소자격리막 내에 도전 물질을 매립함으로써, 선택되지 않은 셀의 스토리지 노드의 퍼텐셜에 의한 선택된 셀의 문턱 전압 변화를 방지할 수 있다. 또한, 전계투과차단막(electric field penetration shield layer)에 바이어스를 인가하여 셀의 문턱 전압을 조절할 수 있고, 따라서 셀 트랜지스터의 채널 도핑 농도를 증가시키지 않아도 원하는 셀 트랜지스터의 문턱 전압을 유지할 수 있고, 채널의 폭에 대한 문턱 전압의 의존도를 최소화 할 수 있다.