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公开(公告)号：KR1020040078869A
公开(公告)日：2004-09-13
申请号：KR1020030034186
申请日：2003-05-28
Applicant: 삼성전자주식회사
IPC: G11C11/15
CPC classification number: H01L27/228 , B82Y10/00 , H01L43/08
Abstract: PURPOSE: A magnetic tunnel junction device and a method for manufacturing the same are provided to remove the requirement for the seed layer formed between the lower electrode and the pinning layer. CONSTITUTION: A magnetic tunnel junction device includes a bottom electrode(69), a pinning layer pattern(71), a pinned layer pattern(73), a tunneling layer pattern(75), a free layer pattern(77), a capping layer pattern(79) and a top electrode(81). The magnetic tunnel junction device is characterized in that the bottom electrode(69) has a root mean square(RMS) surface roughness is less than 5Å.
Abstract translation: 目的：提供一种磁性隧道结装置及其制造方法，以消除对形成在下电极和钉扎层之间的晶种层的要求。 构造：磁隧道结装置包括底电极（69），钉扎层图案（71），钉扎层图案（73），隧道层图案（75），自由层图案（77），封盖层 图案（79）和顶部电极（81）。 磁性隧道结装置的特征在于，底部电极（69）的均方根（RMS）表面粗糙度小于5。
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公开(公告)号：KR100428790B1
公开(公告)日：2004-04-28
申请号：KR1020020006192
申请日：2002-02-04
Applicant: 삼성전자주식회사
IPC: H01L27/105
Abstract: PURPOSE: A ferroelectric memory device having an extended plate line and a method for fabricating the same are provided to maximize a contact area between a plate line and an upper electrode and improve an insulating characteristic between the plate line and a main word line. CONSTITUTION: An isolation layer(53) is formed on a semiconductor substrate(51). A plurality of insulated gate electrodes(57) are formed across the isolation layer(53). An active region is divided into one common drain region(61d) and two source regions(61s). A lower interlayer dielectric(74) is deposited on a whole surface of the above structure. A plurality of contact plugs(75) are connected with the source regions(61s). A ferroelectric capacitor(82) is arranged on the whole surface of the above structure. The ferroelectric capacitor(82) includes a lower electrode(77), a ferroelectric layer pattern(79), and an upper electrode(81). An insulating layer pattern(85a) are formed on a gap region between the ferroelectric capacitors(82). A local plate line(87) is formed on the ferroelectric capacitor(82) and the insulating layer pattern(85a). The first and the second upper interlayer dielectric(89,93) are deposited thereon. A main word line(91) is inserted between the first and the second upper interlayer dielectric(89,93). A main plate line(97) is connected with the local plate line(87) through a slit type via hole(95).
Abstract translation: 目的：提供一种具有扩展板线的铁电存储器件及其制造方法，以使板线与上电极之间的接触面积最大化并且改善板线与主字线之间的绝缘特性。 构成：隔离层（53）形成在半导体衬底（51）上。 隔离层（53）上形成多个绝缘栅电极（57）。 有源区被分成一个公共漏极区（61d）和两个源极区（61s）。 在上述结构的整个表面上沉积下层间电介质（74）。 多个接触塞（75）与源极区（61s）连接。 在上述结构的整个表面上设置铁电电容器（82）。 铁电电容器82包括下电极77，铁电层图形79和上电极81。 在铁电电容器（82）之间的间隙区域上形成绝缘层图形（85a）。 局部板线（87）形成在铁电电容器（82）和绝缘层图案（85a）上。 第一和第二上层间电介质（89,93）沉积在其上。 主字线（91）插入在第一和第二上层间电介质（89,93）之间。 主板线（97）通过狭缝型通孔（95）与局部板线（87）连接。
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公开(公告)号：KR1020030013587A
公开(公告)日：2003-02-15
申请号：KR1020010047667
申请日：2001-08-08
Applicant: 삼성전자주식회사
IPC: H01L27/105
CPC classification number: H01L27/11502 , G11C11/22 , H01L27/11507 , H01L28/57
Abstract: PURPOSE: A ferroelectric memory device is provided to recover ferroelectric deterioration of a capacitor ferroelectric layer by performing a post-treatment process, and to prevent an operation error caused by an increase of contact interfacial resistance of the ferroelectric memory device by avoiding oxidation of an adhesive layer pattern between a capacitor lower electrode and a contact plug. CONSTITUTION: The ferroelectric memory device has a cell capacitor pattern in which the adhesive layer pattern(30), a lower electrode, a ferroelectric layer pattern(50) and an upper electrode(60) are sequentially formed. An oxygen barrier pattern(70) is so formed to cover only the sidewall of the cell capacitor pattern under the interface between the lower electrode and the ferroelectric layer pattern.
Abstract translation: 目的：提供一种强电介质存储装置，通过进行后处理工艺来回收电容器铁电层的铁电劣化，并且通过避免粘合剂的氧化来防止强电介质存储装置的接触界面电阻增加引起的操作误差 电容器下电极和接触插头之间的层图案。 构成：铁电存储元件具有依次形成粘接层图案（30），下电极，铁电层图案（50）和上电极（60）的电池电容图案。 氧阻挡图案（70）被形成为仅覆盖在下电极和铁电层图案之间的界面下的电池电容器图案的侧壁。
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公开(公告)号：KR101501578B1
公开(公告)日：2015-03-11
申请号：KR1020080109502
申请日：2008-11-05
Applicant: 삼성전자주식회사
IPC: H04B1/06
CPC classification number: H04L27/3863
Abstract: I신호와 Q신호의 미스매치를 보상할 수 있는 수신기 및 이를 포함하는 통신시스템이 개시된다. 상기 수신기는 다중밴드 주파수 신호에 기초하여 상기 다중밴드 주파수 신호의 동상 신호와 직교 위상 신호를 발생하는 주파수 변환부; 및 상기 다중밴드 주파수 신호의 밴드별로 상이하게 나타나는 상기 동상 신호와 상기 직교 위상 신호의 미스매치를 상기 밴드별로 추정하고 추정된 미스매치를 보상하기 위한 적어도 하나의 보상값을 저장하는 미스매치 보상부를 포함하며, 상기 주파수 변환부는, 상기 적어도 하나의 보상값에 기초하여 상기 동상 신호와 상기 직교 위상 신호의 상기 미스매치를 보상할 수 있다.
다중 밴드, I신호, Q신호, 미스매치, 수신기-
公开(公告)号：KR1020100092662A
公开(公告)日：2010-08-23
申请号：KR1020090011903
申请日：2009-02-13
Applicant: 삼성전자주식회사
CPC classification number: Y02D70/00 , H04B1/71635 , H04L27/2626 , H04W52/0261
Abstract: PURPOSE: An ultra-wideband communication apparatus including a dynamic frequency scaling function for a low power mode is provided to prevent the performance of the apparatus from deteriorating by variously regulating a data transmitting sub-carrier. CONSTITUTION: A transmitting unit(100) converts data stream to be transmitted in a pre-set orthogonal frequency division multiplexing symbol. A dynamic frequency scaling unit(200) selects a power mode based on information from a required transmitting rate, a low power mode state, the remained amount of a battery. The dynamic frequency scaling unit changes the clock frequency of the transmitting unit based on the selected power mode.
Abstract translation: 目的：提供一种包括用于低功率模式的动态频率缩放功能的超宽带通信设备，以通过不同地调节数据传输子载波来防止设备的性能恶化。 构成：发送单元（100）将要发送的数据流转换成预先设定的正交频分复用符号。 动态频率缩放单元（200）基于来自所需传输速率，低功率模式状态，电池剩余量的信息来选择功率模式。 动态频率缩放单元基于所选择的功率模式改变发送单元的时钟频率。
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Patent Agency Ranking
公开(公告)号：KR1020100050283A
公开(公告)日：2010-05-13
申请号：KR1020080109502
申请日：2008-11-05
Applicant: 삼성전자주식회사
IPC: H04B1/06
CPC classification number: H04L27/3863
Abstract: PURPOSE: A receiver capable of compensating mismatch of I-signal and Q-signal and a communication system thereof are provided to maintain the phase difference to the 90 degrees. CONSTITUTION: An ADC(Analog-Digital Converter)(18) analog-digital converts an I(In-phase) signal and Q(Quadruple-phase) signal and outputs the digital signal of I and Q signals. A mismatch compensator(21) presumes the mismatch of Q and I digital signals per each band and stores a digital compensation value for compensating the presumed mismatch. A demodulator(20) compensates the mismatch of I and Q digital signals based on the digital compensation value and performs the demodulation based on the compensation result.
Abstract translation: 目的：提供能够补偿I信号和Q信号失配的接收机及其通信系统，以将相位差保持在90度。 构成：ADC（模拟数字转换器）（18）模拟数字转换I（同相）信号和Q（四相）信号，并输出I和Q信号的数字信号。 不匹配补偿器（21）假设每个频带的Q和I数字信号不匹配，并存储用于补偿推定的不匹配的数字补偿值。 解调器（20）基于数字补偿值补偿I和Q数字信号的不匹配，并且基于补偿结果执行解调。
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公开(公告)号：KR1020060016913A
公开(公告)日：2006-02-23
申请号：KR1020040065381
申请日：2004-08-19
Applicant: 삼성전자주식회사
IPC: H04N7/015
CPC classification number: H04L25/022 , H04L25/0232 , H04L27/2647 , H04L2025/03414
Abstract: DVB-T 수신기에서, 일반적으로 채널 평가는 분산 파일럿들을 통한 시간 도메인 보간 및 주파수 도메인 보간을 통해 완성된다. 시간 도메인 보간 뒤, 주파수 도메인 보간을 완료하기 위해 일반적으로 변환 도메인의 실수성분(real) 로우 패스 필터가 사용된다. 0dB 에코 채널에서, 채널 평가가 취급할 수 있는 0dB 에코의 지연 시간은 주파수 도메인 보간에 의해 제한된다. 실수성분 로우 패스 필터를 사용하는 주파수 도메인 보간이 취급할 수 있는 0dB의 최대 지연 시간은, NorDig 조건의 요구사항 보다 더 작은, 나이키스트 샘플링 정리를 만족시켜야 한다. 본 발명에서, 주파수 도메인 보간이 취급할 수 있는 0dB의 최대 지연 시간은, 변환 도메인의 복소(complex) 필터를 이용하여 증대될 수 있고, NorDig의 요구사항도 DVB-T 수신기 내의 발명을 이용하여 만족될 수 있다.
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公开(公告)号：KR1020040047540A
公开(公告)日：2004-06-05
申请号：KR1020030045784
申请日：2003-07-07
Applicant: 삼성전자주식회사
IPC: H01L27/105
Abstract: PURPOSE: A ferroelectric memory device is provided to solve a problem caused by conventional misalignment by continuously patterning a protecting glue layer and an interlayer dielectric, and to prevent a void and a lifting phenomenon caused by a conventional interface reaction by completely isolating a lower electrode and a ferroelectric layer from an interlayer dielectric thereunder by the protecting glue layer. CONSTITUTION: A semiconductor substrate(100) is prepared. An interlayer dielectric(110) and a protecting glue layer(120) are sequentially formed, including a contact hole(125) for exposing the semiconductor substrate. A buried contact(130) electrically contacts the semiconductor substrate through the contact hole. A part of the protecting glue layer near the buried contact is covered with a lower electrode(140) that overlaps the buried contact. The lower electrode and the protecting glue layer are covered with a ferroelectric layer(150). The ferroelectric layer is covered with an upper electrode(160) that overlaps the lower electrode.
Abstract translation: 目的：提供一种强电介质存储装置，通过连续图案化保护胶层和层间电介质来解决由常规未对准引起的问题，并通过完全隔离下电极和防止由常规界面反应引起的空隙和提升现象， 来自其中的层间电介质的铁电层由保护胶层。 构成：制备半导体衬底（100）。 依次形成层间电介质（110）和保护胶层（120），包括用于暴露半导体衬底的接触孔（125）。 埋入触点（130）通过接触孔与半导体衬底电接触。 掩埋触点附近的保护胶层的一部分被与埋入触点重叠的下电极（140）覆盖。 下电极和保护胶层被铁电层（150）覆盖。 铁电层被与下电极重叠的上电极（160）覆盖。
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公开(公告)号：KR100420121B1
公开(公告)日：2004-03-02
申请号：KR1020010035430
申请日：2001-06-21
Applicant: 삼성전자주식회사
Inventor： 이규만
IPC: H01L27/105
CPC classification number: H01L28/55 , H01L21/31053 , H01L21/31691 , H01L21/3212 , H01L27/11502 , H01L28/60
Abstract: A ferroelectric memory device has bottom electrode patterns formed on a semiconductor substrate, first ferroelectric layer on the substrate and disposed between the electrode patterns, and second ferroelectric layer formed on a top surface of the electrode pattern and a top surface of the first layer. An independent claim is also included for a method of fabricating the ferroelectric memory device.
Abstract translation: 铁电存储器件具有形成在半导体衬底上的底部电极图案，衬底上的第一铁电层以及设置在电极图案之间的第一铁电层以及形成在电极图案的顶部表面和第一层的顶部表面上的第二铁电层。 制造铁电存储器件的方法也包括独立权利要求。
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公开(公告)号：KR1020030073262A
公开(公告)日：2003-09-19
申请号：KR1020020012737
申请日：2002-03-09
Applicant: 삼성전자주식회사
IPC: H05K1/02
CPC classification number: G11C5/02
Abstract: PURPOSE: A component arrangement structure is provided to allow for ease of memory expansion and stable operation of rambus interface, while reducing the height of the module. CONSTITUTION: A rambus memory device including a Vitesse rambus controller(100), a rambus DRAM, a rambus channel and a direct rambus clock generator(DRCG) is disposed on a printed circuit board. The Vitesse rambus controller is spaced apart from a rambus socket(210) mounted on the printed circuit board by 1.5 inches or shorter. The direct rambus clock generator which is capable of operating to the frequency of 800MHz, is spaced apart from the rambus socket by 3 inches or longer.
Abstract translation: 目的：提供一种组件布置结构，以便在减少模块高度的同时，便于存储器扩展和Rambus接口的稳定运行。 构成：在印刷电路板上设置包括Vitesse rambus控制器（100），Rambus DRAM，Rambus通道和直接rambus时钟发生器（DRCG）的Rambus存储器件。 Vitesse rambus控制器与安装在印刷电路板上的1.5英寸或更短的Rambus插座（210）间隔开。 能够操作到800MHz频率的直接rambus时钟发生器与Rambus插座间隔3英寸或更长。
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