公开(公告)号：KR1020080068411A

公开(公告)日：2008-07-23

申请号：KR1020070006190

申请日：2007-01-19

Applicant: 삼성전자주식회사

Inventor： 박상용 ,  박재관 ,  곽동화 ,  황병준 ,  심재황

IPC: H01L21/768

CPC classification number: H01L21/76804

Abstract: A semiconductor device and a method for manufacturing the same are provided to reduce a leakage current to an active region by exposing a semiconductor substrate in a line pattern for forming a contact for a bit line. A semiconductor device includes a semiconductor substrate(100), a plurality of contacts, a plurality of conductive lines, and an inter layer dielectric. Active regions are defined on the semiconductor substrate by a device isolation layer(102). The plurality of contacts are contacted with the active regions, respectively. Each of the contacts has a trapezoid shape, in which the width thereof becomes larger as it goes to a lower portion thereof. The plurality of conductive lines are aligned on the respective contacts. The inter layer dielectric is filled between the contacts. The active regions are formed parallel with each other.

Abstract translation: 提供一种半导体器件及其制造方法，用于通过将用于形成位线的触点的线图案中的半导体衬底曝光来减少到有源区的漏电流。 半导体器件包括半导体衬底（100），多个触点，多个导电线以及层间电介质。 有源区通过器件隔离层（102）限定在半导体衬底上。 多个触点分别与有源区接触。 每个触点具有梯形形状，其宽度随着它的下部变大而变大。 多个导线在各个触点上对准。 层间电介质被填充在触点之间。 有源区域彼此平行地形成。

公开(公告)号：KR1020080036498A

公开(公告)日：2008-04-28

申请号：KR1020070032826

申请日：2007-04-03

Applicant: 삼성전자주식회사

Inventor： 권성현 ,  심재황 ,  곽동화 ,  김주영

IPC: H01L21/28

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/11524

Abstract: A method of fabricating a semiconductor device having fine contact holes is provided to obtain openings of a mask pattern, each having uniform size and secure uniform resistance of contact plugs filling contact holes, by forming first and second molding patterns by patterning first and second molding lines. A method of fabricating a semiconductor device having fine contact holes comprises the steps of: forming an isolation layer(121) defining active regions(118a) on a semiconductor substrate(100); forming an interlayer insulating layer(139) on the semiconductor substrate having the isolation layer; forming a plurality of first molding lines(148) on the interlayer insulating layer; forming a plurality of second molding lines(154) which are located between the first molding lines and spaced away from the first molding lines; patterning the first and second molding lines to form first and second molding patterns; forming a mask pattern surrounding sidewalls of the first and second molding patterns; removing the first and second molding patterns to form openings; and etching the interlayer insulating layer using the mask pattern as an etching mask to form contact holes.

Abstract translation: 提供一种制造具有精细接触孔的半导体器件的方法，以通过使第一和第二成型线图案形成来形成第一和第二成型图案，从而获得具有均匀尺寸并且确保接触塞填充接触孔的均匀电阻的掩模图案的开口 。 制造具有精细接触孔的半导体器件的方法包括以下步骤：在半导体衬底（100）上形成限定有源区（118a）的隔离层（121）; 在具有隔离层的半导体衬底上形成层间绝缘层（139）; 在所述层间绝缘层上形成多个第一成型线（148）; 形成位于所述第一成型线之间并与所述第一成型线分开的多个第二成型线（154） 图案化第一和第二模制线以形成第一和第二模制图案; 形成围绕所述第一和第二模制图案的侧壁的掩模图案; 去除第一和第二模制图案以形成开口; 并使用掩模图案作为蚀刻掩模蚀刻层间绝缘层以形成接触孔。

公开(公告)号：KR100812239B1

公开(公告)日：2008-03-10

申请号：KR1020060101957

申请日：2006-10-19

Applicant: 삼성전자주식회사

Inventor： 곽동화 ,  박재관 ,  심재황 ,  김진호 ,  김기남

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

Abstract: A semiconductor device and a method of manufacturing the same are provided to increase a degree of integration by improving a structure. An insulating layer(50) is formed on a substrate(10) including a plurality of first regions and a plurality of second regions arranged between the first regions. A plurality of first wirings are electrically connected through a first contact to the first regions. A spacer(93) is formed on lateral surfaces of the first wirings. A plurality of contact holes are formed by removing the insulating layer between the adjacent spacers to expose the second regions corresponding to the first contacts. The corresponding contact holes are filled with a plurality of second contacts. A plurality of second wirings are electrically connected to the second contacts.

Abstract translation: 提供了一种半导体器件及其制造方法，以通过改进结构来增加集成度。 在包括多个第一区域和布置在第一区域之间的多个第二区域的基板（10）上形成绝缘层（50）。 多个第一布线通过第一接触电连接到第一区域。 间隔件（93）形成在第一布线的侧表面上。 通过去除相邻间隔物之间​​的绝缘层以暴露对应于第一触点的第二区域来形成多个接触孔。 相应的接触孔填充有多个第二接触件。 多个第二布线电连接到第二触点。

公开(公告)号：KR1020060112534A

公开(公告)日：2006-11-01

申请号：KR1020050035091

申请日：2005-04-27

Applicant: 삼성전자주식회사

Inventor： 심재황 ,  문창록

IPC: H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14636 ,  H01L27/14667

Abstract: An image sensor is provided to avoid a tint defect like a color mixture by effectively preventing or reducing crosstalk. A photoelectric conversion part is formed in a substrate(400). A multilayered intermetal dielectric(420) is formed on the substrate. A light guide part(450) whose upper surface is opened is formed in a region overlapping the photoelectric conversion part of the intermetal dielectric, penetrating the intermetal dielectric. A heterogeneous insulation layer(440,445) is formed along the inner wall of the light guide part, having a different index of refraction from that of the intermetal dielectric. The inside of the light guide part is filled with an insulation layer(430) having a different index of refraction from those of the intermetal dielectric and the heterogeneous insulation layer. The insulation layer has an index of refraction greater than that of the intermetal dielectric, and the heterogeneous insulation layer has an index of refraction greater than that of the insulation layer.

Abstract translation: 提供图像传感器以通过有效地防止或减少串扰来避免像混色的色调缺陷。 在基板（400）上形成光电转换部。 在衬底上形成多层金属间电介质（420）。 在与金属间电介质的光电转换部分重叠的区域中形成有上表面打开的导光部（450），穿过金属间电介质。 沿着导光部分的内壁形成不均匀的绝缘层（440,445），其具有与金属间电介质折射率不同的折射率。 导光部分的内部填充有与金属间电介质和非均匀绝缘层的折射率不同的折射率的绝缘层（430）。 绝缘层的折射率大于金属间电介质的折射率，异质绝缘层的折射率大于绝缘层的折射率。