公开(公告)号：KR1020030050803A

公开(公告)日：2003-06-25

申请号：KR1020010081325

申请日：2001-12-19

Applicant: 한국전자통신연구원

Inventor： 변경진 ,  최민석 ,  정희범 ,  김경수

IPC: G10L19/16 ,  H04B1/40

Abstract: PURPOSE: A method for operating a vocoder for a mobile communication terminal is provided to easily adjust encoding and decoding points of the vocoder through a microprocessor. CONSTITUTION: A vocoder initializes necessary parameters. The vocoder enters a standby state waiting a frame reference signal for setting a timing with a system. The vocoder reads values of encoding offset register(34), decoding offset register(35), and decoding interrupt register(36) preliminarily stored at a microprocessor(33) for initializing IS_CNT and OS_CNT values, and changes a state to operate according to the timing of the system. The vocoder inspects the OS_CNT value. In the case of a decoding point, the vocoder starts decoding. In the case of a non-decoding point, the vocoder inspects the IS_CNT value. In the case of an encoding point, the vocoder starts encoding. In the case of a non-encoding point, the vocoder enters into an idle state.

Abstract translation: 目的：提供一种用于操作用于移动通信终端的声码器的方法，以便通过微处理器容易地调节声码器的编码和解码点。 声明：声码器初始化必要的参数。 声码器进入等待帧参考信号的待机状态，用于设置系统的定时。 声码器读取预先存储在微处理器（33）处的初始化IS_CNT和OS_CNT值的编码偏移寄存器（34），解码偏移寄存器（35）和解码中断寄存器（36）的值，并且根据 系统的时间安排 声码器检查OS_CNT值。 在解码点的情况下，声码器开始解码。 在非解码点的情况下，声码器检查IS_CNT值。 在编码点的情况下，声码器开始编码。 在非编码点的情况下，声码器进入空闲状态。

公开(公告)号：KR1020030027321A

公开(公告)日：2003-04-07

申请号：KR1020010060467

申请日：2001-09-28

Applicant: 한국전자통신연구원 ,  브이케이 주식회사

Inventor： 김익균 ,  김경수

IPC: H04N19/42 ,  H04N19/625

CPC classification number: G06F17/141

Abstract: PURPOSE: A distributed arithmetic processing apparatus and method and a two-dimensional discrete cosine transform processing system and method using the same are provided to reduce power consumption. CONSTITUTION: A discrete cosine transform processing system includes a multiplexer(201) for selecting one of an external input and an input from a transposition memory, the first converter(202) for converting serial data output from the multiplexer into parallel data, and a storage for loading the data output from the first converter in parallel to temporarily store the data. The system further includes an operation unit for performing operations required for discrete-cosine-transform /inverse-discrete-cosine-transform of the data output from the storage, a zero input detector for checking data inputted to the operation unit to pass the data without passing through a part of modules of the operation unit when all of predetermined input bits are "0", and the second converter for converting parallel data output from the operation unit into serial data. The system also includes a rounding and clipping module(233) for carrying out rounding and clipping in order to output the data output from the second converter.

Abstract translation: 目的：提供一种分布式运算处理装置和方法以及二维离散余弦变换处理系统及其使用方法，以降低功耗。 构成：离散余弦变换处理系统包括用于从转置存储器中选择外部输入和输入中的一个的多路复用器（201），用于将从多路复用器输出的串行数据转换成并行数据的第一转换器（202） 用于并行地加载从第一转换器输出的数据以临时存储数据。 该系统还包括用于执行从存储器输出的数据进行离散余弦变换/反离散余弦变换所需的操作的操作单元，用于检查输入到操作单元的数据的零输入检测器，以通过数据而不 当所有预定输入位都为“0”时，通过操作单元的一部分模块，以及用于将从操作单元输出的并行数据转换成串行数据的第二转换器。 该系统还包括用于执行舍入和削波的舍入和限幅模块（233），以便输出从第二转换器输出的数据。

公开(公告)号：KR100371139B1

公开(公告)日：2003-02-07

申请号：KR1019990062457

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 김경수 ,  심재찬 ,  고병도

IPC: H04L12/50

Abstract: PURPOSE: A cross-point element structure for an ATM(Asynchronous Transfer Node) switch is provided to implement a switch having a self-routing function, remove necessity of an additional function for copying a cell, and prevent a time slot from being wasted when the cell is copied. CONSTITUTION: Output-group address inputs(AGN(15:0)) represent the output port grouping address information inputted from an external output address allocation part. Output-group address outputs(AGN(15:0)) are transferred to next switch element via a switch element. A path set status input(SIN) represents a path set status of an upper switch element in the same column. A path set status output(SOUT) informs a path set status output to a lower switch element in the same column. Input-cell address inputs(RGN(15:0)) is received by switch elements. Modification address outputs(MGN(15:0)) transfers the path set status of a switch element to a right switch element. A connection designator(GIN) transmits timing information in order to illustrate a final status.

Abstract translation: 目的：提供一种用于ATM（异步传输节点）交换机的交叉点元件结构，以实现具有自路由功能的交换机，消除了复制单元的附加功能的必要性，并防止当时隙被浪费时 该单元格被复制。 构成：输出组地址输入（AGN（15：0））表示从外部输出地址分配部分输入的输出端口分组地址信息。 输出组地址输出（AGN（15：0））通过开关元件传送到下一个开关元件。 路径设置状态输入（SIN）表示同一列中的上部开关元件的路径设置状态。 路径设置状态输出（SOUT）通知路径设置状态输出到同一列中的下部开关元件。 输入单元地址输入（RGN（15：0））由开关元件接收。 修改地址输出（MGN（15：0））将开关元件的路径设置状态传送到右开关元件。 连接指示符（GIN）传输定时信息以说明最终状态。

公开(公告)号：KR1020030008768A

公开(公告)日：2003-01-29

申请号：KR1020010043670

申请日：2001-07-20

Applicant: 한국전자통신연구원 ,  유티스타콤코리아 유한회사

Inventor： 장성철 ,  유병한 ,  김경수

IPC: H04L12/24

CPC classification number: H04W72/12 ,  H04W72/044

Abstract: PURPOSE: A method for managing resources in a resource managing block of an IMT-2000 asynchronous control station is provided to manage resources through a block managing step and a task managing step, and to configure usable tasks by dual connection structures, thereby assigning traffic channels within a short time. CONSTITUTION: When a control station receives a traffic channel assigning request by a voice call(400), one block of 'svr1Hd' is selected in a block storage space(410). A traffic channel of the next pointer having a dual connection structure is selected and assigned in a task storage space of the selected block(411). If the 'svr1Hd' does not exist at all, one of 'svr2Hd' blocks is selected(420). A traffic channel of a next pointer having a dual connection structure is selected and assigned in a task storage space of the selected block(421). If usable 'svr2Hd' block does not exist, an 'svr3Hd' block is selected(431). If usable 'svr3Hd' block does not exist, an 'al1Hd' block is selected(440), and a usable task is assigned(441). If usable 'al1Hd' block does not exist, a call request is ignored(450). When a resource is assigned, a dual link configuration is updated(460). If a remaining capacity is '0', the block is deleted from the dual connection structure(490).

Abstract translation: 目的：提供一种用于管理IMT-2000异步控制站的资源管理块中的资源的方法，通过块管理步骤和任务管理步骤来管理资源，并通过双连接结构配置可用任务，从而分配业务信道 在短时间内。 构成：当控制站通过语音呼叫（400）接收到业务信道分配请求时，在块存储空间（410）中选择一个“svr1Hd”块。 具有双连接结构的下一个指针的业务信道被选择并分配给所选块的任务存储空间（411）。 如果“svr1Hd”根本不存在，则选择“svr2Hd”块之一（420）。 具有双连接结构的下一个指针的业务信道被选择并分配给所选块的任务存储空间（421）。 如果可用的“svr2Hd”块不存在，则选择“svr3Hd”块（431）。 如果可用的“svr3Hd”块不存在，则选择“al1Hd”块（440），并分配可用任务（441）。 如果可用的“al1Hd”块不存在，则忽略呼叫请求（450）。 当分配资源时，更新双链路配置（460）。 如果剩余容量为0，则从双连接结构（490）中删除该块。

公开(公告)号：KR100341398B1

公开(公告)日：2002-06-22

申请号：KR1020000003873

申请日：2000-01-27

Applicant: 한국전자통신연구원

Inventor： 변경진 ,  김경수 ,  조한진

IPC: H03M7/42

Abstract: 디지털 방식의 휴대용 통신기기에서는 전송채널의 대역폭을 효율적으로 사용하고 또한 고음질을 얻기 위해 여러가지 음성 압축 알고리즘 들을 이용하여 구현된 보코더(vocoder)를 사용하고 있다. 이러한 보코더 기법들 중 비교적 저 전송률의 이동통신 단말기 등에 유용하게 적용하고 있는 것 중에 하나는 CELP(Code Excited Linear Prediction) 부호화법이다. CELP부호화법에서는 음성신호의 단기 예측 및 장기 예측 성분이 제거된 잔여 신호를 부호화하기 위해 고정 코드북 검색과정을 적용하고 있다. 그러나 종래의 코드북 검색에서는 입력음성과 합성음성의 오차를 구하기 위해, 코드북 인덱스 값을 1씩 증가 시키면서 전체 코드북에 대한 검색을 반복하기 때문에 코드북 검색부분은 CELP부호화법에서 필요로 하는 전체 계산량의 50%이상을 차지하므로 실시간 구현에 어려움이 있다.
따라서 본 발명에서는 기존의 코드북 검색 과정과 같이 모든 인덱스에 대해 반복적으로 코드북 검색을 하지 않고 새로운 최소오차 값을 찾은 경우에 카운터 값이 증가하는 최소 오차 카운터를 적용하여, 카운터의 값이 일정 값을 초과하는 경우에는 검색을 종료하는 방법을 사용하여 기존의 코드북 검색시간을 약 68%정도로 단축하는 새로운 방법을 제공한다.

公开(公告)号：KR1020020025468A

公开(公告)日：2002-04-04

申请号：KR1020000057316

申请日：2000-09-29

Applicant: 한국전자통신연구원

Inventor： 이호석 ,  어익수 ,  김경수 ,  조한진

IPC: H04B1/709 ,  H04J13/20

CPC classification number: H04B1/709 ,  H04B1/7117 ,  H04J13/20 ,  H04L1/0631

Abstract: PURPOSE: A demodulator using an STTD(Space Time black coding based Transmit antenna Diversity) decoder for spread spectrum communication is provided to include the STTD decoder for supporting an STTD decoding, and to use one multiplier and one integrator in the STTD decoder, so as to reduce the size and easily perform a variable signal processing by controlling operations of the STTD decoder according to an STTD mode. CONSTITUTION: A code generator(203) is composed of many spread code generators and OVSF(Orthogonal Variable Spreading Factor) code generators. A complex despreader(302) is connected to a channel predictor(213) for outputting many predicted channels, and complex-despreads spread spectrum signals which are sampled at a low speed by using spread codes. A backward channelizer(305) backward-channelizes the despread signals by using OVSF codes. A summer(307) integrates output signals of the backward channelizer(305) as symbol units according to a chip rate enable signal, and outputs the integrated signals. Serial to parallel converters(310,311) store the integrated symbol values of the summer(307), and divide even-numbered and odd-numbered symbols as two-symbol units, then output the divided symbols. An STTD decoder(315) selectively receives the predicted channels and signals of two symbols buffered in the serial to parallel converters(310,311), to perform a complex multiplication, and performs a channel distortion compensation and an STTD decoding. A deskew buffer(321) stores signals decoded in the STTD decoder(315) by arranging time.

Abstract translation: 目的：提供一种使用STTD（空时黑色编码的发射天线分集）解调器进行扩频通信的解调器，包括用于支持STTD解码的STTD解码器，并在STTD解码器中使用一个乘法器和一个积分器，以便 通过根据STTD模式控制STTD解码器的操作来减小尺寸并容易地执行可变信号处理。 构成：代码生成器（203）由许多扩展码发生器和OVSF（正交可变扩频因子）码发生器组成。 复解调器（302）连接到用于输出许多预测信道的信道预测器（213），并且通过使用扩频码对以低速采样的扩频信号进行复扩展。 反向信道化器（305）通过使用OVSF码对解扩信号进行反向信道化。 夏季（307）根据码片使能信号将反向信道化器（305）的输出信号作为符号单位进行积分，并输出积分信号。 串行到并行转换器（310,311）存储加法器（307）的积分符号值，并将偶数和奇数符号划分为双符号单位，然后输出划分的符号。 STTD解码器（315）选择性地接收在串行到并行转换器（310,311）中缓冲的两个符号的预测通道和信号，以执行复数乘法，并执行信道失真补偿和STTD解码。 偏移缓冲器（321）通过布置时间来存储在STTD解码器（315）中解码的信号。

公开(公告)号：KR1020010047388A

公开(公告)日：2001-06-15

申请号：KR1019990051589

申请日：1999-11-19

Applicant: 한국전자통신연구원

Inventor： 임인기 ,  이석호 ,  김경수 ,  조한진

IPC: H04L27/20

CPC classification number: H04L27/2071

Abstract: PURPOSE: A QPSK modulation apparatus and method using multi-bit input RF filter for 4 channels is provided to reduce hardware by half by designing 2 FIR filters processing operations of 4 one bit input 1:4 interpolation FIR filter simultaneously. CONSTITUTION: A pseudo noise(PN) spreading device(304) divides one bit data inputted from 4 channels and divides and PN spreads them to generate 8 one bit data. Two FIR filtering device(305,306) are supplied with the 8 one bit data and execute filtering for pulse shaping. A plurality of multiplier(307-314) multiply the filtering outputs from the FIR filtering device by each gain for the channels and outputs n-bit data. A plurality of adder(315-320) QPSK-modulate the n-bit data output from the multiplier and output I channel signal and Q channel signal.

Abstract translation: 目的：提供4通道多位输入RF滤波器的QPSK调制装置和方法，通过同时设计4个1位4位1：4插值FIR滤波器的2个FIR滤波器处理操作，将硬件减少一半。 构成：伪噪声（PN）扩展装置（304）对从4个信道输入的一个比特数据进行分割，并对它们进行扩频，生成8个一位数据。 两个FIR滤波装置（305,306）被提供8位一位数据，并执行脉冲整形滤波。 多个乘法器（307-314）将来自FIR滤波装置的滤波输出乘以通道的每个增益，并输出n位数据。 多个加法器（315-320）对从乘法器输出的n位数据进行QPSK调制，并输出I通道信号和Q通道信号。

公开(公告)号：KR1020010010636A

公开(公告)日：2001-02-15

申请号：KR1019990029625

申请日：1999-07-21

Applicant: 한국전자통신연구원

Inventor： 김경수 ,  채종억 ,  고병도

IPC: H04L12/00

CPC classification number: H04L49/105 ,  H04L12/5601 ,  H04L49/3081

Abstract: PURPOSE: An ATM switching apparatus using a byte interleaving method is provided to increase switching capacity of a switching structure by providing a byte interleaving manner with a switching fabric having constant switching capacity. CONSTITUTION: An ATM switching apparatus comprises an input line driving unit(110) which removes noise of a control signal and data to push the signal and the data to intelligent peripheral interface unit(120). An output line drive unit(150) transmits an output signal to adjacent card line. The unit(120) senses receiving of a cell in response to a cell enable signal and a cell start signal of a cell input to the unit(110). The unit(120) compares a routing tag loaded on upper and lower bits to store the tag in an input buffer when identical. An upper and a lower switching fabric(131,132) divide data input to the unit(110) into an upper and a lower bit, and switches the divided bits into corresponding output ports in synthesization with a cell synchronous signal so as to be converted and output. An output port controller(140) receives cell enable signals corresponding to the upper and lower bits from the fabrics(131,132), and stores the upper and lower data bits in an output buffer by a byte interleaving manner when the enable signals have the same condition.

Abstract translation: 目的：提供一种使用字节交织方法的ATM交换设备，通过与具有恒定交换容量的交换结构提供字节交织方式来提高交换结构的交换容量。 构成：ATM交换装置包括：消除控制信号的噪声的输入线驱动单元（110）和将信号和数据推送到智能外设接口单元（120）的数据。 输出线驱动单元（150）将输出信号发送到相邻的卡线。 单元（120）响应于单元使能信号和输入到单元（110）的单元的单元开始信号来感测单元的接收。 当相同时，单元（120）比较加载在高位和低位上的路由标签，以将标签存储在输入缓冲器中。 上，下交换结构（131,132）将输入到单元（110）的数据分成上位和下位，并且用单元同步信号合成将分割位转换成对应的输出端，以便转换和输出 。 输出端口控制器（140）从结构（131,132）接收与上位和下位相对应的单元使能信号，并且当使能信号具有相同条件时，通过字节交织方式将上和下数据位存储在输出缓冲器中 。

公开(公告)号：KR100276083B1

公开(公告)日：2000-12-15

申请号：KR1019970071614

申请日：1997-12-22

Applicant: 한국전자통신연구원

Inventor： 김욱 ,  권종기 ,  이종렬 ,  오창준 ,  송원철 ,  김경수

IPC: H03L7/00

Abstract: PURPOSE: A frequency dividing device for low noise of frequency composer is provided to perform low phase noise property by adding extra latch to output end of frequency divider and isolating power source line from other lines. CONSTITUTION: A time delay circuit(100) delays input clock signal for a time. A frequency divider(200) divides signal delayed in the time delay circuit(100). A D-flipflop(300) is connected to output side of the frequency divider(200), and takes input clock signal inputted to the time delay circuit(100) as clock and eliminates delay time of the frequency divider(200) according to input signal of the frequency divider(200). The delay time of the time delay circuit(100) is prior to the time latched in the D-flipflop(300) in case that total input signal is output in the frequency divider(200).

Abstract translation: 目的：提供频率合成器低噪声的分频装置，通过向分频器的输出端增加额外的锁存器，并将电源线与其他线路隔离来提供低相位噪声性能。 时间延迟电路（100）延迟输入时钟信号一段时间。 分频器（200）对延迟电路（100）中延迟的信号进行分频。 D触发器（300）连接到分频器（200）的输出侧，并将输入到时间延迟电路（100）的输入时钟信号作为时钟，并根据输入消除分频器（200）的延迟时间 分频器（200）的信号。 在分频器（200）中输出总输入信号的情况下，时间延迟电路（100）的延迟时间在D触发器（300）中锁存的时间之前。

公开(公告)号：KR100268648B1

公开(公告)日：2000-10-16

申请号：KR1019970032659

申请日：1997-07-14

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 송원철 ,  이종렬 ,  오창준 ,  권종기 ,  김욱 ,  김경수

IPC: H03H9/46

CPC classification number: H03H11/04

Abstract: PURPOSE: A low frequency filter is provided to allow a low frequency filter having a cut frequency(3fdB) in a very low frequency(within several hundreds of Hz) to be built into a chip by using an active resistor having a very large resistance and a capacitor of several pF. CONSTITUTION: A low frequency filter includes a capacitor of a small capacity connected between an input terminal and an output terminal of the low frequency filter. A filter circuit(110A) includes an active resistor having a transistor of a dynamic resistance characteristic inputted to the output terminal of the capacitor and operating as a current source. The filter circuit(110A) functions to filter the inputted signal and to cut low frequency signals. A bias circuit(110B) is connected to an active resistor of the filter circuit(110A) and negative-feedbacks an output voltage of the active resistor being an output voltage of the filter circuit(110A) by means of the transistor of a dynamic resistance characteristic operating as the current source of a structure such as the active resistor. The filter circuit(110A) and the bias circuit(110B) are built in a semiconductor chip.

Abstract translation: 目的：提供一种低频滤波器，通过使用具有非常大电阻的有源电阻器，将具有非常低频率（几百Hz）内的切割频率（3fdB）的低频滤波器内置到芯片中， 几个pF的电容器。 构成：低频滤波器包括连接在低频滤波器的输入端子和输出端子之间的小容量电容器。 滤波器电路（110A）包括具有输入到电容器的输出端子并作为电流源工作的动态电阻特性的晶体管的有源电阻器。 滤波器电路（110A）用于对输入信号进行滤波并切断低频信号。 偏置电路（110B）连接到滤波电路（110A）的有源电阻器，并通过动态电阻晶体管对有源电阻器的输出电压作为滤波电路（110A）的输出电压进行负反馈 特性作为诸如有源电阻器的结构的电流源操作。 滤波器电路（110A）和偏置电路（110B）内置在半导体芯片中。