公开(公告)号：NO922092L

公开(公告)日：1992-11-30

申请号：NO922092

申请日：1992-05-26

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40 ,  G06F13/20

Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.

公开(公告)号：NO922090L

公开(公告)日：1992-11-30

申请号：NO922090

申请日：1992-05-26

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00 ,  G06F9/02

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

公开(公告)号：NO922090A

公开(公告)日：1992-11-30

申请号：NO922090

申请日：1992-05-26

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00 ,  G06F9/02

CPC classification number: G06F1/24

公开(公告)号：FI922351A

公开(公告)日：1992-11-29

申请号：FI922351

申请日：1992-05-22

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.

公开(公告)号：NO922090D0

公开(公告)日：1992-05-26

申请号：NO922090

申请日：1992-05-26

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00 ,  G06F

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

公开(公告)号：AU6375790A

公开(公告)日：1991-05-09

申请号：AU6375790

申请日：1990-10-03

Applicant: IBM

Inventor： LYFORD AVERY MARTIN ,  MOELLER DENNIS LEE ,  KLIM PETER JUERGEN

IPC: G06F9/48 ,  G06F13/24 ,  G06F13/26 ,  G06F13/36

Abstract: A programmable interrupt controller (8) having a plurality of interrupt request inquest inputs (42, 56)and an interrupt request output (58) for connection to a central processing unit (4) (CPU) includes means for interrupting the CPU (4) over the interrupt request output (58) responsive to an interrupt request from any one of the interrupt request inputs (42, 56) and a priority resolver (92) for assigning a priority position to each of the interrupt request inputs (42, 56) to create an interrupt priority hierarchy. The interrupt controller (8) is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register (94) of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register (94) to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

公开(公告)号：HK81590A

公开(公告)日：1990-10-19

申请号：HK81590

申请日：1990-10-11

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F9/46 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.

公开(公告)号：PH24588A

公开(公告)日：1990-08-17

申请号：PH31371

申请日：1984-10-26

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F13/28 ,  G06F9/00

Abstract: A microcomputer system includes a main processor (1), a memory (3) and a direct memory access controller (DMA;4) effective to control direct data transfer between the memory and input / output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line (27) from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means co-act with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.

公开(公告)号：BE1001067A3

公开(公告)日：1989-06-27

申请号：BE8701440

申请日：1987-12-16

Applicant: IBM

Inventor： LO YUAN-CHANG ,  MOELLER DENNIS LEE ,  SZAREK JOHN JOSEPH

IPC: G06F12/16 ,  G06F11/22 ,  G06F12/06 ,  G11C29/00 ,  G06F

Abstract: Un système de micro-ordinateur comporte des premiers moyens de mémoire d'adresses d'ordre inférieur soudés au panneau de circuits imprimés plan et peut accepter d'autres moyens de mémoire enfichables dans des moyens de connexion sur le panneau. Sous alimentation, en auto-test, on teste les moyens de mémoire et si une erreur est détectée dans le premier moyen de mémoire, ce moyen de mémoire est déconditionné en dirigeant les adresses de mémoire d'ordre le plus bas aux seconds moyens de mémoire et en réduisant les adresses d'ordre le plus élevé du nombre des emplacements dans les premiers moyens de mémoire.

公开(公告)号：GB2156113A

公开(公告)日：1985-10-02

申请号：GB8432313

申请日：1984-12-20

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F13/28 ,  G06F13/32

Abstract: A microcomputer system includes a main processor (1), a memory (3) and a direct memory access controller (DMA;4) effective to control direct data transfer between the memory and input / output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line (27) from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means co-act with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.