公开(公告)号：WO0247157A3

公开(公告)日：2003-01-30

申请号：PCT/US0144920

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMA ,  KUDELKA STEPHAN ,  LEE KIL-HO ,  MCSTAY IRENE ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01L21/763 ,  H01L21/8234

CPC classification number: H01L27/10867

Abstract: A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

Abstract translation: 用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。 在沟槽填充材料上形成薄膜，氮化硅，阻挡层。 在阻挡层上沉积非晶硅掩模层的薄膜。 对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。 从深沟槽剥离非晶硅掩模层的未掺杂部分。 然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。 反映出暴露部分的沟槽填充材料。 氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

公开(公告)号：WO0141201A9

公开(公告)日：2002-05-30

申请号：PCT/US0032471

申请日：2000-11-27

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： FALTERMEIER JOHNATHAN E ,  GRUENING ULRIKE ,  HEGDE SURYANARAYAN ,  JAMMY RAJARAO ,  LEE BRIAN S ,  TEWS HELMUT

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/12 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/28211 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  Y10S438/931

Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a (100) crystal plane and a (110) crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the (110) crystal plane of the trench side wall, but not into the (100) crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Abstract translation: 一种用于制造垂直晶体管的栅极氧化物的工艺。 在第一步骤中，在衬底中形成沟槽，沟槽从衬底的顶表面延伸并且具有沟槽底部和沟槽侧壁。 沟槽侧壁包括（100）晶面和（110）晶面。 接下来，在沟槽侧壁上形成均匀厚度的牺牲层。 在形成牺牲层之后，通过牺牲层注入氮离子，使得氮离子注入到沟槽侧壁的（110）晶面中，但不注入沟槽侧壁的（100）晶面。 然后去除牺牲层，并且沟槽侧壁被氧化以形成栅极氧化物。

公开(公告)号：DE10246306B4

公开(公告)日：2009-05-07

申请号：DE10246306

申请日：2002-10-04

Applicant: IBM ,  QIMONDA AG

Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01G4/06 ,  H01L21/316 ,  H01L21/321

Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

公开(公告)号：DE10214743A1

公开(公告)日：2004-11-04

申请号：DE10214743

申请日：2002-04-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KNORR ANDREAS ,  KUDELKA STEPHAN ,  MANDELMAN JACK ,  RAHN STEPHAN ,  TEWS HELMUT ,  WISE MICHAEL

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108