公开(公告)号：WO0247157A3

公开(公告)日：2003-01-30

申请号：PCT/US0144920

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMA ,  KUDELKA STEPHAN ,  LEE KIL-HO ,  MCSTAY IRENE ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01L21/763 ,  H01L21/8234

CPC classification number: H01L27/10867

Abstract: A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

Abstract translation: 用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。 在沟槽填充材料上形成薄膜，氮化硅，阻挡层。 在阻挡层上沉积非晶硅掩模层的薄膜。 对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。 从深沟槽剥离非晶硅掩模层的未掺杂部分。 然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。 反映出暴露部分的沟槽填充材料。 氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

公开(公告)号：WO0203455A3

公开(公告)日：2002-06-13

申请号：PCT/US0120913

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JAMMY RAJARAO ,  FALTERMEIER CHERYL G ,  SCHROEDER UWE ,  WONG KWONG HON

IPC: C23C16/04 ,  C23C16/34 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L21/76843 ,  C23C16/045 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/76852 ,  H01L21/7687 ,  H01L27/10861 ,  H01L28/82

Abstract: Process for forming highly conformal titanium nitride on a silicon substrate. A gaseous reaction mixture of titanium tetrachloride and ammonia is passed over the semiconductor substrate surface maintained at a temperature of about 350 DEG C to about 800 DEG C. The r atio of titanium tetrachloride to ammonia is about 5:1 to 20:1. The high degree of conformality achieved by the process of the invention allows TiN layers to be deposited on structures with high aspect ratios and on complicated, three-dimensional structures without forming a large seam or void.

Abstract translation: 在硅衬底上形成高保形氮化钛的工艺。 将四氯化钛和氨的气态反应混合物通过保持在约350℃至约800℃温度的半导体衬底表面。四氯化钛与氨的反应混合物为约5：1至20：1。 通过本发明的方法实现的高度的保形性允许TiN层沉积在具有高纵横比的结构上和复杂的三维结构上，而不形成大的接缝或空隙。

公开(公告)号：WO0245134A3

公开(公告)日：2003-04-03

申请号：PCT/US0151214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HORN PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/60 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Abstract translation: 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：DE60133214D1

公开(公告)日：2008-04-24

申请号：DE60133214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：WO0199185A3

公开(公告)日：2002-03-28

申请号：PCT/US0119576

申请日：2001-06-19

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN S ,  MICHAELIS ALEXANDER ,  KUDLEKA STEPHAN ,  SCHROEDER UWE

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/10876

Abstract: A method of forming a vertically-oriented device such as a DRAM storage all with a trench capacitor under a vertical transistor, using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a poertion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Abstract translation: 使用选择性湿法蚀刻仅在沟槽中除去一部分侧壁，以及由其形成的器件，在垂直晶体管下，用沟槽电容器形成诸如DRAM存储器的垂直取向器件的方法。 虽然沟槽周边（例如，隔离环304）的作用被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的基板 侧壁（324）与单晶面。 单侧垂直沟槽晶体管可以形成在平坦侧壁上。 形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。 此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

公开(公告)号：WO0189284A3

公开(公告)日：2002-05-30

申请号：PCT/US0115896

申请日：2001-05-16

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  MICHAELIS ALEXANDER ,  KUDELKA STEPHEN ,  SCHROEDER UWE ,  GRUENING ULRIKE

IPC: H01L21/8242

CPC classification number: H01L27/10861

Abstract: A method of using at least two insulative layers to form the isolation collar of a trench capacitor, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

Abstract translation: 使用至少两个绝缘层形成沟槽电容器的隔离环的方法，以及由其形成的器件。 第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。 优选地，TEOS工艺和LOCOS工艺都用于形成第一层。 第二层优选是形成在氧化物层上的氮化硅层（114）。 多层用作沟槽的隔离环叠层。 第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

公开(公告)号：WO0199162A3

公开(公告)日：2002-07-18

申请号：PCT/US0119882

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MICHAELIS ALEXANDER ,  TEWS HELMUT HORST ,  KUDELKA STEPHAN ,  GRUENING ULRIKE ,  BEINTNER JOCHEN ,  SCHROEDER UWE

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28211 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of using a selective etch to provide a desired crystal plane orientation on the sidewalls of a deep trench located in a semiconductor substrate, and the device formed therefrom. Preferably, a crystal plane sidewall (212) is used for the channel region, and crystal planes (216) are used in the corner regions of the trench. Gate oxidation may then be performed such that the oxide is thicker in the corner regions (222) than on the oxide (218, 220) on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area (224). In addition, the structure is relatively insensitive to active area/deep trench misalignment.

Abstract translation: 一种使用选择性蚀刻以在位于半导体衬底中的深沟槽的侧壁上提供期望的晶面取向的方法和由其形成的器件。 优选地，在沟道区域中使用<100>晶面侧壁（212），并且在沟槽的拐角区域中使用<110>晶面（216）。 然后可以执行栅极氧化，使得在角区域（222）中的氧化物比在沟槽的初级侧上的氧化物（218,220）上更厚，导致拐角区域与晶体管沟道/活性物质的自我隔离 区域（224）。 此外，该结构对有源区/深沟槽未对准相对不敏感。

公开(公告)号：WO0191180A3

公开(公告)日：2002-07-18

申请号：PCT/US0115757

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN S ,  MICHAELIS ALEXANDER ,  SCHROEDER UWE ,  KUDELKA STEPHEN

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L27/10864 ,  H01L21/76237 ,  H01L21/823487 ,  H01L27/10841 ,  H01L27/10867

Abstract: A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

Abstract translation: 使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。 电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。 低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。 然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。 然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分 沟槽暴露进一步加工。 或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。 自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

公开(公告)号：DE10261330A1

公开(公告)日：2003-08-14

申请号：DE10261330

申请日：2002-12-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  KUDELKA STEPHAN P ,  SCHROEDER UWE ,  MCSTAY IRENE LENNOX ,  RAHN STEPHEN

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242

Abstract: In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising:a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon;b) depositing a SiN liner on said collar region and on the region below the collar;c) depositing a layer of a-Si on the SiN liner to form a micromask;d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks;e) subjecting the SiN liner to an etch selective to SiO;f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface;g) stripping SiO and the SiN; and forming a node and collar deposition.

公开(公告)号：DE10258201B4

公开(公告)日：2008-07-03

申请号：DE10258201

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： RAJARAO JAMMY ,  KUDELKA STEPHAN ,  MACSTAY IRENE ,  RAHN STEPHEN ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/8242