公开(公告)号：US20220222340A1

公开(公告)日：2022-07-14

申请号：US17711883

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Vidhya Krishnan ,  Ankur Shah ,  Bryan White ,  Daniel Nemiroff ,  David Puffer ,  Julien Carreno ,  Scott Janus ,  Ravi Sahita ,  Hema Nalluri ,  Utkarsh Y. Kakaiya

IPC: G06F21/55 ,  G06F21/54 ,  G06F21/60 ,  G06F9/50

Abstract: Security and support for trust domain operation is described. An example of a method includes processing, at an accelerator, one or more compute workloads received from a host system; upon receiving a notification that a trust domain has transitioned to a secure state, transition an original set of privileges for the accelerator to a downgraded set of privileges; upon receiving a command from the host system for the trust domain, processing the command in accordance with the trust domain; and upon receiving a request from the host system to access a register, for a register included in an allowed list of registers for access, allow access to the register, and, for a register that is not within the allowed list of registers for access, disallowing access to the register.

公开(公告)号：US20220207293A1

公开(公告)日：2022-06-30

申请号：US17482875

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Scott Janus ,  Sungye Kim

IPC: G06K9/62 ,  G06T11/00

Abstract: Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.

公开(公告)号：US20220197800A1

公开(公告)日：2022-06-23

申请号：US17428539

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek Appu ,  Lakshminarayanan Striramassarma ,  Altug Koker ,  Sean Coleman ,  Varghese George ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Elmoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Karthik Vaidyanathan

IPC: G06F12/0811 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/0866 ,  G06F12/0891 ,  G06F12/0882 ,  G06F12/02 ,  G06F12/06

Abstract: Graphics processors of the present design provide hierarchical open sectors and variable cache sizes for cache operations. In one embodiment, a graphics processor comprises a cache memory having a hierarchical open sector design including a first hierarchy of upper and lower regions with each region including a second hierarchy of sectors. A cache controller is configured to initially open a first sector of the lower region, to receive a memory request that does not match an address in the first sector, and to open a second sector of the lower region.

公开(公告)号：US20220179787A1

公开(公告)日：2022-06-09

申请号：US17428530

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/0802 ,  G06F9/30

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US20220156202A1

公开(公告)日：2022-05-19

申请号：US17590362

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC: G06F12/123 ,  G06F12/0891 ,  G06T1/60 ,  G06F12/0875

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

公开(公告)号：US20220138286A1

公开(公告)日：2022-05-05

申请号：US17133336

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： David Zage ,  Scott Janus ,  Ned M. Smith ,  Vidhya Krishnan ,  Siddhartha Chhabra ,  Rajesh Poornachandran ,  Tomer Levy ,  Julien Carreno ,  Ankur Shah ,  Ronald Silvas ,  Aravindh Anantaraman ,  David Puffer ,  Vedvyas Shanbhogue ,  David Cowperthwaite ,  Aditya Navale ,  Omer Ben-Shalom ,  Alex Nayshtut ,  Xiaoyu Ruan

IPC: G06F21/10 ,  G06F21/60 ,  G06T1/20 ,  G06F9/455

Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.

公开(公告)号：US20220107914A1

公开(公告)日：2022-04-07

申请号：US17429873

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ben Ashbaugh ,  Scott Janus ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Niranjan Cooray ,  Varghese George ,  Arthur Hunter ,  Brent E. Insko ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Surti Prasoonkumar ,  Saurabh Tangri

IPC: G06F15/78

Abstract: Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

公开(公告)号：US11113784B2

公开(公告)日：2021-09-07

申请号：US17064427

申请日：2020-10-06

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Andrei Valentin ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, Jr. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06T1/20 ,  G06F9/50 ,  G06F15/80 ,  G06F12/0806 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06F7/544

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

公开(公告)号：US11062500B2

公开(公告)日：2021-07-13

申请号：US16236041

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Scott Janus ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Philip Laws

IPC: G06T15/00 ,  G06T15/06 ,  G06T17/00

Abstract: Apparatus and method for ray tracing acceleration using a grid primitive. For example, one embodiment of an apparatus comprises: a grid primitive generator to generate a grid primitive comprising a plurality of adjacent interconnected primitives; a bitmask generator to generate a bitmask associated with the grid primitive, the bitmask comprising a plurality of bitmask values, each mask value associated with a primitive of the grid primitive; a ray tracing engine comprising traversal and intersection hardware logic to perform traversal and intersection operations in which rays are traversed through a hierarchical acceleration data structure and intersections between the rays and one or more of the adjacent interconnected primitives identified, wherein the ray tracing engine is to read the bitmask to determine a first set of primitives from the grid primitive on which to perform the traversal and intersection operations and a second set of primitives from the grid primitive on which the traversal and intersection operations will not be performed.

公开(公告)号：US20180301095A1

公开(公告)日：2018-10-18

申请号：US15488602

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: G09G3/34 ,  G09G3/36 ,  B60R1/00

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.