公开(公告)号：WO2010042496A3

公开(公告)日：2010-07-22

申请号：PCT/US2009059669

申请日：2009-10-06

Applicant: MICRON TECHNOLOGY INC ,  KEETH BRENT ,  MARTIN CHRIS G ,  MANNING TROY A ,  JEDDELOH JOE M ,  COWLES TIMOTHY B ,  REHMEYER JIM ,  LABERGE PAUL A

Inventor： KEETH BRENT ,  MARTIN CHRIS G ,  MANNING TROY A ,  JEDDELOH JOE M ,  COWLES TIMOTHY B ,  REHMEYER JIM ,  LABERGE PAUL A

IPC: G11C8/04 ,  G11C8/06

CPC classification number: G06F12/08 ,  G06F12/10 ,  G11C5/025 ,  G11C29/04 ,  G11C29/18 ,  G11C29/76 ,  G11C29/78 ,  G11C29/808 ,  G11C29/812 ,  G11C29/883 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.

Abstract translation: 各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

公开(公告)号：WO02073619A9

公开(公告)日：2003-12-18

申请号：PCT/US0207226

申请日：2002-03-12

Applicant: MICRON TECHNOLOGY INC

Inventor： JANZEN JEFFERY W ,  BRENT KEETH ,  RYAN KEVIN J ,  MANNING TROY A ,  JOHNSON BRIAN

IPC: G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G06F13/42 ,  G11C7/20 ,  G11C11/4067 ,  G11C11/4072 ,  G11C11/4076

CPC classification number: G11C7/22 ,  G11C7/1072

Abstract: In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

Abstract translation: 在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。 本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统 读延迟。

公开(公告)号：WO9839845A3

公开(公告)日：2000-09-14

申请号：PCT/US9804281

申请日：1998-03-05

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: H03K21/00 ,  H03K23/00 ,  H03K23/44 ,  H03K23/54

CPC classification number: H03K23/44 ,  H03K23/54

Abstract: A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input and output stages, each having two sets of switches. The first set of switches in each stage provides a supply voltage to a stage output in response to the asymmetrical clocks. The second set of switches supply ground to the stage output in response to the asymmetrical clocks. To accelerate response of the switching circuits, isolation switches decouple the first set of switches in each pair from the stage output during switching of the second set of switches, thereby removing loading of stage output by the second set of switches.

Abstract translation: 计数器电路包括由两个相移时钟驱动的一系列寄存器。 计数器电路中的时钟发生器产生四个非对称时钟信号来驱动每个寄存器。 寄存器由输入和输出级形成，每级具有两组开关。 每个级中的第一组开关响应于不对称时钟向电平输出提供电源电压。 第二组开关响应不对称时钟向地面输出提供接地。 为了加速开关电路的响应，隔离开关在第二组开关切换期间将每一对中的第一组开关与级输出分离，从而消除第二组开关的输出负载。

公开(公告)号：EP3243137A4

公开(公告)日：2018-08-01

申请号：EP16735388

申请日：2016-01-07

Applicant: MICRON TECHNOLOGY INC

Inventor： WHEELER KYLE B ,  MURPHY RICHARD C ,  MANNING TROY A ,  KLEIN DEAN A

IPC: G06F12/02 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10

CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：EP3039685A4

公开(公告)日：2017-05-31

申请号：EP14839348

申请日：2014-08-13

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C7/10 ,  G06F12/02 ,  G06F12/06 ,  G11C7/06 ,  G11C8/10 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C15/00 ,  G11C15/04

CPC classification number: G11C8/10 ,  G06F9/30 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0888 ,  G06F13/40 ,  G06F2212/7202 ,  G11C7/06 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/419 ,  G11C15/04 ,  G11C2207/2245 ,  Y02D10/13

Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

Abstract translation: 本公开的示例提供了用于访问存储器阵列地址空间的设备和方法。 一种示例存储器阵列，包括：第一地址空间，包括耦合到第一数量的选择线和多个感测线的存储器单元;以及第二地址空间，包括耦合到第二数量的选择线和多个感测线的存储器单元 。 第一地址空间相对于第二地址空间是可独立寻址的。

公开(公告)号：EP3025346A4

公开(公告)日：2017-03-29

申请号：EP14829677

申请日：2014-07-10

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C15/04 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

公开(公告)号：EP1312091A4

公开(公告)日：2006-02-15

申请号：EP02721442

申请日：2002-03-12

Applicant: MICRON TECHNOLOGY INC

Inventor： KEETH BRENT ,  JOHNSON BRAIN ,  MANNING TROY A

IPC: G11C7/00 ,  G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops (120). In the high speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters (150a), which transfrom the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals (160). In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters (150a), which transfrom the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective on of 8 data bus terminals (160).

公开(公告)号：EP3127120A4

公开(公告)日：2017-11-15

申请号：EP15774178

申请日：2015-03-26

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C15/043 ,  G11C7/1006 ,  G11C11/4091

Abstract: Apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.

公开(公告)号：EP2965316A4

公开(公告)日：2017-01-18

申请号：EP14760332

申请日：2014-02-20

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C7/06 ,  G06F15/78 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C15/00

CPC classification number: G11C7/065 ,  G06F12/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C15/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

公开(公告)号：EP2825960A4

公开(公告)日：2016-01-06

申请号：EP13762035

申请日：2013-03-08

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A ,  LARSEN TROY D ,  CULLEY MARTIN L

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/00 ,  G06F13/14 ,  G11C29/42

CPC classification number: G06F11/1068 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/44 ,  G06F11/108 ,  G06F2211/104 ,  G11C29/52

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.