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    72.
    发明专利
    未知

    公开(公告)号：FR2817982B1

    公开(公告)日：2003-10-24

    申请号：FR0016035

    申请日：2000-12-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS ,  MURILLO LAURENT

    IPC: G06F11/20 ,  G11C7/00 ,  G11C29/00

    Abstract: An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

    74.
    发明专利
    未知

    公开(公告)号：DE69907800D1

    公开(公告)日：2003-06-18

    申请号：DE69907800

    申请日：1999-03-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： HARRAND MICHEL ,  FERRANT RICHARD

    IPC: G11C7/10 ,  G11C7/00

    Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.

    Shared redundancy integrated circuit memory, uses allocation circuits associated with memory banks to switch input/output lines
    75.
    发明专利
    Shared redundancy integrated circuit memory, uses allocation circuits associated with memory banks to switch input/output lines 未知

    公开(公告)号：FR2817982A1

    公开(公告)日：2002-06-14

    申请号：FR0016035

    申请日：2000-12-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS ,  MURILLO LAURENT

    IPC: G06F11/20 ,  G11C7/00 ,  G11C29/00

    Abstract: Each allocation circuit (20) associated with memory bank (B) has means to switch the input/output lines (IOLi) as well as conductors (CTRL) for individual activation of read amplifiers (SA) of concerned memory bank. The allocation circuits comprise input/output line switches (IOLi) formed in same metallic level. The input/output lines and activation conductors (CTRL) are also formed in same metallic level. The lines and conductors are interrupted to right of each allocation circuit. Integrated memory circuit having at least two banks (B) each having a matrix of memory elements having at least a redundancy column and each associated with its own read amplifiers (SA); a row of input/output buffer circuits common to the memory banks; each memory bank has an allocation circuit (20), for the redundancy column, top an input/output line (IOLi) connected to one of the buffers. Allocation can be effected, for a line of a current row, towards the preceding row of columns and towards the following row of columns.

    77.
    发明专利
    未知

    公开(公告)号：FR2797117B1

    公开(公告)日：2001-10-12

    申请号：FR9910043

    申请日：1999-07-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: H03K3/012 ,  H03K3/03 ,  H03B5/32

    Abstract: The oscillator with quartz crystal (10) comprises an inverter (8) with complementary transistors (MN1, MP1) connected between high (Vdd) and low (GND) potentials of power supply by the intermediary of two resistances, which are constituted by lossy capacitors (18C, 20C) with higher than normal leakage currents, and an amplifier (22) for delivering logic stages according to output levels of the oscillator. The amplifier (22) comprises a number of stages, each containing two transistors with opposite conductivity type channels connected in series between high and low potentials of power supply, where the gate of first transistor of each stage is connected to the output of preceding stage, and the gates of second transistors of two consecutive stages are connected respectively to the input and the output of the inverter (8).

    79.
    发明专利
    未知

    公开(公告)号：FR2785080A1

    公开(公告)日：2000-04-28

    申请号：FR9813546

    申请日：1998-10-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： JAOUEN HERVE ,  FERRANT RICHARD

    IPC: G11C11/401 ,  H01L21/8242 ,  H01L27/108

    Abstract: The cell memory of dynamic random access type comprises a MOS (metal-oxide-silicon) transistor and a capacitor in monolithic structure with the second electrode (311) common to all cells of the same row covered with an insulating layer (312), and comprising independent conducting elements (313-1,313-2) mutually spaced in the same horizontal plane and alternatively high and low polarized. The low potential is the reference potential of the memory circuit equal to e.g. that of the ground. The high potential is the writing potential equal to e.g. the supply potential Vdd. The second electrode (311) is made up of a metallic layer of e.g. tungsten, and a conducting layer of e.g. polycrystalline silicon. The insulating layer (312) is of e.g. silicon oxide. The equivalent capacitance of the memory circuit is in the form of three decoupling capacitors connected in a triangle; the first and second capacitors are formed between the second electrode (311) and the first and the second conducting elements, respectively; the third capacitor is formed between the first and the second elements (313-1) and (313-2). In the case of the conducting elements with a surface of size 1.55 micrometer by 2.8 micrometer, and the insulating layer of thickness 9 micrometer, the three capacitances are: 145 pF, 166 pF, and 166 pF.

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